{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9818666","patent":{"patent_number":"US-9818666","title":"Interconnect arrangement with stress-reducing structure and method of fabricating the same","assignee":null,"inventors":[],"filing_date":"2016-10-17T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Interconnect arrangement with stress-reducing structure and method of fabricating the same","description":"A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9818666","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9818666","citation_suggestion":"Patentable. \"Interconnect arrangement with stress-reducing structure and method of fabricating the same\" (US-9818666). https://patentable.app/patents/US-9818666","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9818666","json":"https://patentable.app/api/llm-context/US-9818666","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:03:06.125Z"}