{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9818730","patent":{"patent_number":"US-9818730","title":"Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement","assignee":null,"inventors":[],"filing_date":"2014-09-04T00:00:00.000Z","publication_date":"2017-11-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":28,"abstract":"A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement","description":"A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assemb","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9818730","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9818730","citation_suggestion":"Patentable. \"Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement\" (US-9818730). https://patentable.app/patents/US-9818730","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9818730","json":"https://patentable.app/api/llm-context/US-9818730","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:05:44.001Z"}