{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9823688","patent":{"patent_number":"US-9823688","title":"Level balanced clock tree","assignee":null,"inventors":[],"filing_date":"2015-04-08T00:00:00.000Z","publication_date":"2017-11-21T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Level balanced clock tree","description":"A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of inter","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9823688","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9823688","citation_suggestion":"Patentable. \"Level balanced clock tree\" (US-9823688). https://patentable.app/patents/US-9823688","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9823688","json":"https://patentable.app/api/llm-context/US-9823688","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:01:58.789Z"}