{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9824013","patent":{"patent_number":"US-9824013","title":"Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors","assignee":null,"inventors":[],"filing_date":"2012-05-08T00:00:00.000Z","publication_date":"2017-11-21T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F"],"num_claims":20,"abstract":"Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors","description":"Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9824013","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9824013","citation_suggestion":"Patentable. \"Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors\" (US-9824013). https://patentable.app/patents/US-9824013","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9824013","json":"https://patentable.app/api/llm-context/US-9824013","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:07:08.422Z"}