{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9825032","patent":{"patent_number":"US-9825032","title":"Metal layer routing level for vertical FET SRAM and logic cell scaling","assignee":null,"inventors":[],"filing_date":"2016-11-23T00:00:00.000Z","publication_date":"2017-11-21T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":14,"abstract":"Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Metal layer routing level for vertical FET SRAM and logic cell scaling","description":"Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting devi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9825032","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9825032","citation_suggestion":"Patentable. \"Metal layer routing level for vertical FET SRAM and logic cell scaling\" (US-9825032). https://patentable.app/patents/US-9825032","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9825032","json":"https://patentable.app/api/llm-context/US-9825032","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:23:26.933Z"}