{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9831000","patent":{"patent_number":"US-9831000","title":"Testing electronic memories based on fault and test algorithm periodicity","assignee":null,"inventors":[],"filing_date":"2014-09-12T00:00:00.000Z","publication_date":"2017-11-28T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C","G11C","G11C"],"num_claims":21,"abstract":"An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Testing electronic memories based on fault and test algorithm periodicity","description":"An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9831000","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9831000","citation_suggestion":"Patentable. \"Testing electronic memories based on fault and test algorithm periodicity\" (US-9831000). https://patentable.app/patents/US-9831000","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9831000","json":"https://patentable.app/api/llm-context/US-9831000","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:48:11.338Z"}