{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9837144","patent":{"patent_number":"US-9837144","title":"Apparatus and method for controlling boost capacitance for low power memory circuits","assignee":null,"inventors":[],"filing_date":"2017-01-17T00:00:00.000Z","publication_date":"2017-12-05T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":22,"abstract":"A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method for controlling boost capacitance for low power memory circuits","description":"A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9837144","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9837144","citation_suggestion":"Patentable. \"Apparatus and method for controlling boost capacitance for low power memory circuits\" (US-9837144). https://patentable.app/patents/US-9837144","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9837144","json":"https://patentable.app/api/llm-context/US-9837144","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:20:15.391Z"}