{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9841807","patent":{"patent_number":"US-9841807","title":"Method and apparatus for a zero voltage processor sleep state","assignee":null,"inventors":[],"filing_date":"2015-12-04T00:00:00.000Z","publication_date":"2017-12-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G06F","G06F","G06F"],"num_claims":24,"abstract":"Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for a zero voltage processor sleep state","description":"Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the proc","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9841807","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9841807","citation_suggestion":"Patentable. \"Method and apparatus for a zero voltage processor sleep state\" (US-9841807). https://patentable.app/patents/US-9841807","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9841807","json":"https://patentable.app/api/llm-context/US-9841807","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:37:40.628Z"}