{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9842630","patent":{"patent_number":"US-9842630","title":"Memory component with adjustable core-to-interface data rate ratio","assignee":null,"inventors":[],"filing_date":"2014-10-02T00:00:00.000Z","publication_date":"2017-12-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":18,"abstract":"A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory component with adjustable core-to-interface data rate ratio","description":"A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the me","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9842630","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9842630","citation_suggestion":"Patentable. \"Memory component with adjustable core-to-interface data rate ratio\" (US-9842630). https://patentable.app/patents/US-9842630","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9842630","json":"https://patentable.app/api/llm-context/US-9842630","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:21:31.930Z"}