{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9842642","patent":{"patent_number":"US-9842642","title":"Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories","assignee":null,"inventors":[],"filing_date":"2015-08-17T00:00:00.000Z","publication_date":"2017-12-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":12,"abstract":"An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories","description":"An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a sta","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9842642","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9842642","citation_suggestion":"Patentable. \"Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories\" (US-9842642). https://patentable.app/patents/US-9842642","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9842642","json":"https://patentable.app/api/llm-context/US-9842642","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:23:17.302Z"}