{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9842652","patent":{"patent_number":"US-9842652","title":"Memory array with power-efficient read architecture","assignee":null,"inventors":[],"filing_date":"2015-12-07T00:00:00.000Z","publication_date":"2017-12-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory array with power-efficient read architecture","description":"Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9842652","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9842652","citation_suggestion":"Patentable. \"Memory array with power-efficient read architecture\" (US-9842652). https://patentable.app/patents/US-9842652","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9842652","json":"https://patentable.app/api/llm-context/US-9842652","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:19:48.034Z"}