{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9846673","patent":{"patent_number":"US-9846673","title":"Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution","assignee":null,"inventors":[],"filing_date":"2012-10-30T00:00:00.000Z","publication_date":"2017-12-19T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":25,"abstract":"It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution","description":"It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9846673","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9846673","citation_suggestion":"Patentable. \"Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution\" (US-9846673). https://patentable.app/patents/US-9846673","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9846673","json":"https://patentable.app/api/llm-context/US-9846673","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:27:27.324Z"}