{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9846755","patent":{"patent_number":"US-9846755","title":"Method for cell placement in semiconductor layout and system thereof","assignee":null,"inventors":[],"filing_date":"2015-04-16T00:00:00.000Z","publication_date":"2017-12-19T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":20,"abstract":"According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for cell placement in semiconductor layout and system thereof","description":"According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a s","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9846755","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9846755","citation_suggestion":"Patentable. \"Method for cell placement in semiconductor layout and system thereof\" (US-9846755). https://patentable.app/patents/US-9846755","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9846755","json":"https://patentable.app/api/llm-context/US-9846755","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:51:14.030Z"}