{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9851401","patent":{"patent_number":"US-9851401","title":"Stacked memory device and semiconductor memory system including the same","assignee":null,"inventors":[],"filing_date":"2016-05-05T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked memory device and semiconductor memory system including the same","description":"Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of inp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9851401","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9851401","citation_suggestion":"Patentable. \"Stacked memory device and semiconductor memory system including the same\" (US-9851401). https://patentable.app/patents/US-9851401","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9851401","json":"https://patentable.app/api/llm-context/US-9851401","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:28:55.202Z"}