{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852039","patent":{"patent_number":"US-9852039","title":"Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices","assignee":null,"inventors":[],"filing_date":"2016-02-03T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":20,"abstract":"An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, and a plurality of PLL-timed physical devices that are identical to the physical devices used in the customer's communication system. A first connector receptacle and a second connector receptacle are coupled to the control logic and to one or more of the PLL-timed physical devices, and are configured to receive a PLL card including a PLL timing device. A third connector receptacle is coupled in series between the first connector receptacle and the second connector receptacle and is configured to receive a backplane emulator card having electrical characteristics emulating a backplane of the customer's communication system."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices","description":"An evaluation board and a method for evaluating Phase Locked Loop (PLL) timing devices. The evaluation board includes an input and output circuit disposed on a circuit board along with control logic, ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852039","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852039","citation_suggestion":"Patentable. \"Phase locked loop (PLL) timing device evaluation system and method for evaluating PLL timing devices\" (US-9852039). https://patentable.app/patents/US-9852039","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852039","json":"https://patentable.app/api/llm-context/US-9852039","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:11:43.897Z"}