{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852091","patent":{"patent_number":"US-9852091","title":"Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels","assignee":null,"inventors":[],"filing_date":"2016-10-26T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an event target number, and a number of bits to ignore. The IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number, the number of bits to ignore, and a process identifier (ID) when the level specified in the ENM corresponds to a user level. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels","description":"A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM). The ENM specifies a level, an ev","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852091","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852091","citation_suggestion":"Patentable. \"Techniques for handling interrupts in a processing unit using virtual processor thread groups and software stack levels\" (US-9852091). https://patentable.app/patents/US-9852091","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852091","json":"https://patentable.app/api/llm-context/US-9852091","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:28:13.060Z"}