{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852790","patent":{"patent_number":"US-9852790","title":"Circuit methodology for highly linear and symmetric resistive processing unit","assignee":null,"inventors":[],"filing_date":"2016-10-26T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G11C","G06N","G06N","G06N","G06N","G06N","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A resistive processing unit (RPU) includes a circuit including at least two current mirrors connected in series, and a capacitor connected with the at least two current mirrors, the capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by one of the at least two current mirrors."},"analysis":{"summary":"The patent **Circuit Methodology for Highly Linear and Symmetric Resistive Processing Unit** (US-9852790) introduces a groundbreaking circuit design for resistive processing units (RPUs), crucial components in advanced artificial intelligence hardware. At its core, this innovation aims to overcome the significant challenges of linearity and symmetry that plague traditional analog AI computation, leading to more precise and energy-efficient AI systems.\n\nThe primary problem this invention solves is the inherent inaccuracy and instability in analog RPU operations. Existing analog circuits often suffer from non-linear weight updates and asymmetric write/erase cycles, which compromise the performance and reliability of neural networks, requiring complex and power-intensive digital compensation. This limits the true potential of analog AI acceleration.\n\nThe key technical approach involves an RPU circuit featuring at least two current mirrors connected in series, along with a capacitor. This capacitor serves as the weight storage element, with its charge level determining the weight. The ingenuity lies in utilizing one of these current mirrors to precisely charge or discharge the capacitor. This controlled current delivery ensures that weight modifications are highly linear, meaning a proportional input yields a proportional output, and perfectly symmetric, ensuring consistent behavior for both increasing and decreasing weights. This level of precision is vital for stable and accurate deep learning operations.\n\nThe business value and applications of this technology are substantial. It enables the development of next-generation AI accelerators that are significantly more energy-efficient and accurate, particularly for inference tasks at the edge and in data centers. This translates to lower operational costs, extended battery life for AI-powered devices, and faster, more reliable processing for complex AI models. Industries such as autonomous vehicles, IoT, cloud computing, and consumer electronics stand to benefit immensely from this hardware innovation.\n\nThe market opportunity is vast, driven by the escalating demand for high-performance, low-power AI solutions. By addressing a fundamental hardware limitation, this invention positions itself as a critical enabler for the widespread adoption of analog and neuromorphic computing. It offers a competitive advantage to semiconductor manufacturers and AI companies seeking to build more capable, sustainable, and scalable AI systems.","layman_explanation":null,"technical_analysis":"The patent, **Circuit Methodology for Highly Linear and Symmetric Resistive Processing Unit** (US-9852790), details a novel circuit architecture designed to enhance the performance and reliability of resistive processing units (RPUs), particularly in the context of artificial intelligence and neuromorphic computing. The core technical challenge addressed is the inherent non-linearity and asymmetry often encountered in analog RPU operations, which can severely degrade the accuracy and efficiency of neural network computations.\n\n**Technical Architecture and Core Components:**\nAt the heart of this invention is an RPU circuit comprising two primary elements: at least two current mirrors connected in series, and a capacitor. The capacitor serves as the memory element, storing a synaptic weight as a charge level. This choice of a capacitor, rather than a memristor, offers distinct advantages in terms of linearity and programmability, though it introduces challenges related to charge retention and write endurance, which the current mirror configuration helps mitigate.\n\n**Implementation Details and Algorithm Specifics:**\n1.  **Current Mirror Configuration:** The patent specifies the use of 'at least two current mirrors connected in series'. A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device, maintaining a high output impedance. Connecting them in series could imply several architectural advantages:\n    *   **Cascaded Precision:** Multiple stages can amplify or refine the control current, leading to higher precision in the current delivered to the capacitor.\n    *   **Differential Control:** A series arrangement might enable a differential drive, which is excellent for common-mode noise rejection and achieving high symmetry.\n    *   **Voltage Compliance:** Series-connected mirrors can potentially extend the voltage compliance range for the capacitor, allowing for a wider dynamic range of stored weights.\n2.  **Capacitor as a Weight Element:** The capacitor's charge level directly represents the weight. This is a crucial design choice. Unlike resistive elements whose resistance changes, a capacitor's charge can be precisely controlled by integrating current over time.\n3.  **Controlled Charging/Discharging:** The innovation lies in how the capacitor is charged or discharged. One of the current mirrors in the series is specifically designated for this task. This current mirror acts as a highly controlled current source or sink. By applying a precise, controlled current for a specific duration, the charge on the capacitor, and thus the weight, can be altered with extreme linearity.\n    *   **Linearity:** The current mirror ensures that the current flowing into or out of the capacitor is stable and independent of the capacitor's instantaneous voltage (within its operating range). This direct proportionality between applied current and charge change guarantees highly linear weight updates, critical for preventing distortion in neural network activations.\n    *   **Symmetry:** For effective training of neural networks, increasing a weight should have the same functional behavior as decreasing it. The current mirror, being a bidirectional current control element, can be designed to provide symmetric charging and discharging characteristics. This means the write-up and write-down operations for a synaptic weight are consistent, preventing biases in learning and improving convergence rates.\n    *   **Weight Update Algorithm:** The implicit algorithm involves applying a pulse of controlled current (from the current mirror) for a defined duration. The magnitude of the current and the duration of the pulse determine the step size of the weight update. For a target weight, the system would iteratively apply these pulses, monitoring the capacitor's charge (or a proxy voltage) until the desired level is reached.\n\n**Performance Characteristics and Integration Patterns:**\nThis methodology promises superior performance characteristics:\n*   **High Precision:** Achieved through linear and symmetric weight updates.\n*   **Energy Efficiency:** Analog computation reduces data movement, and precise control minimizes energy wasted on error correction.\n*   **Fast Operation:** Direct analog computation can be significantly faster than digital for matrix operations.\n*   **Robustness:** The controlled nature of current mirrors can offer better immunity to process variations and environmental noise compared to passive resistive elements.\n\nIntegration with existing digital systems would likely involve analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) at the periphery of the RPU array to interface with digital controllers and memory. The RPU array would function as a highly efficient analog compute engine, offloading complex matrix operations from the main digital processor.\n\n**Code-Level Implications:**\nFrom a software perspective, this technology simplifies the underlying neural network training and inference frameworks. Developers would no longer need to implement complex hardware-aware quantization or non-linearity compensation algorithms as extensively as with less precise analog hardware. This allows for cleaner, more direct mapping of neural network models onto the hardware, potentially leading to faster development cycles and improved software-hardware co-design. The enhanced linearity and symmetry would also mean that standard backpropagation algorithms could be applied more directly, without significant modifications to account for hardware imperfections. This invention represents a significant step towards truly robust and efficient analog AI computing.","business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Circuit methodology for highly linear and symmetric resistive processing unit","description":"A resistive processing unit (RPU) includes a circuit including at least two current mirrors connected in series, and a capacitor connected with the at least two current mirrors, the capacitor providin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852790","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852790","citation_suggestion":"Patentable. \"Circuit methodology for highly linear and symmetric resistive processing unit\" (US-9852790). https://patentable.app/patents/US-9852790","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852790","json":"https://patentable.app/api/llm-context/US-9852790","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:47:02.077Z"}