{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852793","patent":{"patent_number":"US-9852793","title":"Methods for programming and accessing DDR compatible resistive change element arrays","assignee":null,"inventors":[],"filing_date":"2016-06-23T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G11C","B82Y","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":24,"abstract":"A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration."},"analysis":{"summary":"The patent Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays introduces a groundbreaking high-speed memory circuit architecture for resistive change element arrays. This innovation addresses the critical need for faster, more efficient non-volatile memory, bridging the performance gap between volatile DRAM and slower flash memory.\n\nThe core problem this patent solves is the challenge of rapidly and reliably reading and programming resistive change elements, particularly when aiming for compatibility with high-speed DDR (Double Data Rate) interfaces. Existing methods often struggle with speed, power consumption, and signal integrity over large arrays.\n\nThis technology's key technical approach involves organizing resistive change elements into rows and columns, with each row uniquely serviced by two bit lines. Crucially, each row includes a pair of precisely calibrated reference elements and a sense amplifier. During a high-speed READ operation, one bit line discharges through the selected memory element, while the other discharges through a reference element. The sense amplifier then compares the *rate* of discharge on these two lines, enabling a much faster and more robust determination of the memory cell's state (SET or RESET) than traditional absolute voltage sensing. Data is transmitted as high-speed synchronized pulses, ensuring DDR compatibility.\n\nFrom a business perspective, this invention offers significant value. It enables the creation of truly persistent main memory, leading to instant-on systems and eliminating data loss during power failures. It also promises substantial performance boosts for applications in high-performance computing, artificial intelligence, edge devices, and enterprise data centers where both speed and data retention are paramount. The DDR compatibility lowers the barrier to adoption, allowing for integration into existing memory ecosystems.\n\nThis presents a substantial market opportunity for semiconductor manufacturers and system integrators. The ability to deploy high-speed, non-volatile memory that meets DDR standards could disrupt existing memory markets and unlock new product categories, driving innovation in computing infrastructure and consumer electronics alike. The Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent is poised to be a foundational technology for the next generation of memory solutions.","layman_explanation":"### What Problem Does This Solve?\nImagine your business relies heavily on data—whether it's for real-time analytics, complex AI models, or simply ensuring your systems boot up instantly. Currently, computer memory has a fundamental trade-off: it's either super-fast but 'forgets' everything when you turn off the power (like your computer's main RAM), or it remembers everything but is much slower (like your hard drive or SSD). This forces businesses to constantly move data between fast, volatile memory and slower, persistent storage, creating a bottleneck that slows down operations, wastes energy, and adds complexity. The problem is a lack of truly 'universal memory' that combines both speed and persistence.\n\n### How Does It Work?\nThe patent, **Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays**, addresses this by innovating how a promising new memory type, called resistive change memory (RRAM), operates. Think of RRAM as tiny switches that can be 'on' or 'off' (representing data) and remember their state even without power. The challenge has been reading these switches fast enough to keep up with modern processors, especially those using DDR (Double Data Rate) technology, which demands incredibly precise timing.\n\nThis innovation introduces a clever way to 'read' the state of these switches. Instead of just checking if a switch is on or off, which can be slow and prone to error, this system uses a 'race' analogy. For each switch it wants to read, it sets up two parallel paths, like two short race tracks. One path includes the actual memory switch, and the other includes a 'reference' switch that's always set to a neutral, known state. The system then simultaneously sends a signal down both paths and measures which one completes its 'race' faster. If the memory switch's path is much faster than the reference, it knows the switch is 'on'. If it's slower, it's 'off'. This comparative 'speed test' is much faster and more reliable than trying to measure the absolute state of a single switch. Crucially, the system is designed to send and receive data in perfectly synchronized bursts, making it fully compatible with existing high-speed DDR memory channels.\n\n### Why Does This Matter?\nThis technology matters because it allows RRAM to perform at speeds comparable to today's fastest memory (DRAM) while retaining its ability to remember data without power. For businesses, this means:\n\n*   **Instant-On Systems:** Servers and devices could boot up in seconds, dramatically reducing downtime and improving efficiency.\n*   **Enhanced Performance:** Applications requiring massive datasets (e.g., AI, big data analytics) could run significantly faster as data access bottlenecks are removed.\n*   **Improved Data Resilience:** Data would persist even during power outages, reducing the risk of data loss and simplifying disaster recovery.\n*   **Reduced Power Consumption:** RRAM is inherently more energy-efficient than DRAM, leading to lower operating costs for data centers.\n*   **Simplified Architecture:** The ability to combine memory and storage functions into a single, high-performance, non-volatile layer can simplify system design and reduce hardware complexity.\n\nThis innovation creates a pathway for truly 'persistent memory' modules that can sit directly on the processor bus, transforming how applications are designed and executed.\n\n### What's Next?\nThis patent lays the groundwork for a new generation of computing. We can expect to see this technology integrated into next-generation enterprise servers, high-performance computing clusters, and specialized AI hardware in the near future. Its adoption could lead to more compact, powerful, and energy-efficient devices, from edge computing nodes to advanced consumer electronics. For investors, this represents a significant opportunity in the burgeoning market for advanced non-volatile memory, with the potential for substantial ROI as this innovation drives widespread industry adoption and new product categories.","technical_analysis":"The patent **Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays** (US-9852793) delineates a sophisticated memory circuit architecture designed to overcome the long-standing challenges of integrating resistive change memory (RRAM) with high-speed, DDR-compatible interfaces. The core technical innovation resides in a meticulously engineered read/program mechanism that leverages differential sensing and synchronized data transfer.\n\n**Technical Architecture:** The memory array is structured as a grid of resistive change elements. A fundamental departure from simpler array designs is the allocation of two dedicated bit lines per row, alongside conventional word lines for column selection. Each row also integrates a sense amplifier and a pair of reference elements. These reference elements are not arbitrary resistors; their electrical resistance values are critically engineered to fall precisely between the SET (low resistance) and RESET (high resistance) states of the active resistive change elements within the array. This intermediate resistance value is crucial for the differential comparison.\n\n**Algorithm Specifics for High-Speed READ:** The high-speed READ operation is the cornerstone of this invention. Upon selection of a specific resistive change element via its word line, the system initiates a differential discharge process. One of the two bit lines associated with that row is connected to the selected resistive change element and begins to discharge through it. Concurrently, the other bit line in the same row is connected to one of the pre-calibrated reference elements and discharges through it. The integrated sense amplifier then performs a rapid comparison of the *rate of voltage discharge* on these two bit lines. Because a SET state (low resistance) will cause a faster discharge than a RESET state (high resistance), and the reference element provides a known intermediate discharge rate, the sense amplifier can quickly and reliably determine the state of the selected memory cell. This method offers significant advantages over absolute voltage sensing, which is prone to noise, temperature drift, and process variations, by focusing on a relative difference that inherently self-calibrates against common-mode disturbances. The output of the sense amplifier is then converted into high-speed synchronized data pulses, ready for transmission to an output data bus, ensuring strict adherence to DDR timing protocols.\n\n**Implementation Details and Integration Patterns:** The integration of the sense amplifier and reference elements directly within each row minimizes signal propagation delays and maximizes sensing speed. This localized sensing approach reduces the need for lengthy global bit lines to carry analog signals to a central sense amplifier block, a common bottleneck in large memory arrays. The synchronized data pulse output facilitates straightforward integration with existing DDR memory controllers and interfaces, requiring minimal modifications to the broader system architecture. The PROGRAM operation mirrors the READ in its high-speed, synchronized nature, receiving external data pulses for efficient writing to the resistive change elements.\n\n**Performance Characteristics:** The differential discharge rate comparison fundamentally accelerates the READ cycle. By avoiding the need to fully charge or discharge a capacitor to a stable voltage level before comparison, and instead comparing dynamic discharge rates, the latency of state detection is significantly reduced. This, coupled with synchronized data transfer, enables access speeds compatible with modern DDR standards, pushing RRAM performance closer to that of DRAM while retaining non-volatility. The robust nature of differential sensing also contributes to higher yield and reliability, as it is less sensitive to manufacturing variations in individual RRAM cells.\n\n**Code-Level Implications:** For system architects and firmware engineers, this technology implies a more predictable and faster interface to persistent memory. While the low-level control of the bit lines, word lines, and sense amplifiers is handled by the hardware architecture, the consistent and high-speed synchronized data interface simplifies driver development. It allows for the treatment of RRAM as a truly high-performance, byte-addressable non-volatile memory, potentially simplifying memory management units and enabling more efficient data structures for persistent data storage. Applications can leverage this innovation for faster checkpointing, instant-on capabilities, and novel in-memory computing paradigms.","business_analysis":"The patent **Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays** represents a pivotal advancement with substantial business implications for the semiconductor and computing industries. By addressing the critical challenge of high-speed interfacing for resistive change memory (RRAM) with DDR standards, this technology is poised to unlock significant market opportunities and redefine competitive landscapes.\n\n**Market Opportunity Size:** The global memory market is vast, projected to reach hundreds of billions of dollars. Within this, the non-volatile memory segment, particularly emerging memory technologies like RRAM, is expected to see rapid growth. This patent specifically targets the high-performance segment, which includes enterprise servers, data centers, AI/ML accelerators, and high-end consumer devices. The ability to provide DDR-compatible RRAM can enable persistent main memory, a market estimated to be worth tens of billions annually in the coming years, as it allows for the convergence of storage and memory functions.\n\n**Competitive Advantages:** The innovation detailed in this patent offers several distinct competitive advantages:\n\n1.  **Performance Lead:** The differential discharge READ operation provides significantly faster access times than many current RRAM sensing schemes, potentially rivaling DRAM speeds while retaining non-volatility. This speed advantage is crucial in performance-sensitive applications.\n2.  **DDR Compatibility:** Seamless integration with existing DDR controllers and infrastructure reduces the barrier to adoption for OEMs and system integrators, offering a 'plug-and-play' advantage over other emerging memory technologies that require entirely new interface designs.\n3.  **Reliability and Endurance:** The robust differential sensing mechanism inherently improves reliability by mitigating the effects of noise and cell variability, leading to higher yield and longer product lifecycles.\n4.  **Power Efficiency:** RRAM generally consumes less power than DRAM. Combining this with an efficient sensing architecture further enhances energy savings, a key selling point for data centers and mobile devices.\n\n**Revenue Potential:** This technology has the potential to generate revenue through several channels:\n\n*   **Licensing:** Semiconductor IP licensing to memory manufacturers and system-on-chip (SoC) designers.\n*   **Product Sales:** Integration into proprietary persistent memory modules (PMMs) or as embedded memory in specialized processors.\n*   **Market Share Capture:** Displacing existing memory solutions (e.g., specific DRAM or enterprise SSD tiers) in applications where the combination of speed, non-volatility, and DDR compatibility is critical.\n\n**Business Models:** Potential business models include a pure IP licensing model, joint ventures with memory foundries, or even vertical integration for specialized high-performance computing solutions. The DDR compatibility makes it attractive for large-scale adoption by established memory players, who can integrate this innovation into their existing product lines with reduced R&D overhead for interface design.\n\n**Strategic Positioning:** This patent positions its assignee as a leader in advanced memory architecture, particularly in the emerging non-volatile memory space. It provides a strong foundation for developing next-generation persistent memory solutions that address current computing bottlenecks. Companies leveraging this innovation can strategically target markets demanding high-speed, always-on data access, such as real-time analytics, artificial intelligence, and cloud infrastructure.\n\n**ROI Projections:** Early adoption in high-value segments like enterprise servers and AI accelerators could demonstrate rapid ROI through improved system performance, reduced total cost of ownership (TCO) from lower power consumption, and enhanced data resilience. As the technology matures and manufacturing scales, its application could expand to broader consumer markets, further accelerating returns. The Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent offers a clear path to commercializing high-performance RRAM.","faqs":[{"answer":"Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays is a patent (US-9852793) that describes a novel high-speed memory circuit architecture. Its primary purpose is to enable efficient programming and access of resistive change elements, often referred to as RRAM or ReRAM, while maintaining compatibility with high-speed DDR (Double Data Rate) interfaces.\n\nThis invention addresses a critical challenge in modern computing: bridging the performance gap between volatile DRAM (fast but temporary) and non-volatile flash memory (persistent but slower). By providing a robust and rapid mechanism for reading and writing data to RRAM arrays, this patent paves the way for a new generation of memory solutions that combine the best attributes of both.\n\nThe technology is designed to make resistive change memory a viable option for applications requiring both high speed and data persistence, such as main memory in servers, AI accelerators, and advanced embedded systems. It represents a significant step forward in the quest for universal memory.","question":"What is Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays?"},{"answer":"The core of Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays lies in its unique memory array organization and a sophisticated differential sensing mechanism for read operations. The resistive change elements are arranged in rows and columns, but each row is serviced by two bit lines, not just one.\n\nCrucially, each row also includes a pair of precisely calibrated reference elements and a sense amplifier. During a high-speed READ operation, one of the row's bit lines is discharged through the selected resistive change element, while simultaneously, the other bit line is discharged through one of the reference elements. The reference elements have a resistance value specifically set between the 'SET' (low resistance) and 'RESET' (high resistance) states of the memory cells.\n\nThe integrated sense amplifier then rapidly compares the *rate* of discharge on these two bit lines. By comparing the dynamic discharge rates rather than static voltage levels, the system can determine the memory cell's state much faster and more reliably. The storage state data is then transmitted as high-speed synchronized data pulses, ensuring compatibility with DDR interfaces. Similarly, PROGRAM operations are designed for high-speed, synchronized data reception for efficient writing.","question":"How does Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays work?"},{"answer":"Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays primarily solves the problem of integrating high-speed, non-volatile resistive change memory (RRAM) with existing DDR-compatible computing systems. Historically, RRAM has struggled to achieve the necessary read/write speeds and reliability to function as main memory, despite its advantages of non-volatility and high density.\n\nTraditional memory architectures are often bottlenecked by the need to move data between fast, volatile DRAM and slower, persistent storage. This patent addresses this 'memory wall' by providing a robust and efficient method for RRAM to operate at speeds comparable to DDR, thus making it a viable candidate for 'persistent memory' – memory that is both fast and retains data after power loss.\n\nThe differential sensing technique outlined in this patent overcomes limitations of prior art, such as slow sensing times, susceptibility to noise, and challenges in maintaining signal integrity across large memory arrays, which were significant barriers to RRAM's widespread adoption in high-performance computing.","question":"What problem does Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays solve?"},{"answer":"The patent Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays (US-9852793) lists specific inventors, though their names are not provided in the prompt data. Patents are typically filed by individuals or teams of inventors who contribute to the novel ideas and designs. The assignee (the entity to whom the patent rights are transferred, usually a company) is also not provided in the prompt.\n\nHowever, the existence of such a patent indicates significant research and development efforts in the field of advanced memory technologies. Innovations like this are often the result of collaborative work within semiconductor companies, research institutions, or university labs focused on pushing the boundaries of computing hardware.\n\nFor a complete list of inventors and the assignee, one would typically refer to the full patent document available through patent databases like the USPTO or Google Patents, using the patent number US-9852793.","question":"Who invented Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays?"},{"answer":"The Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent offers several key benefits that are set to revolutionize memory technology:\n\n1.  **Ultra-High Speed Access:** The differential discharge rate comparison method significantly accelerates read operations, allowing RRAM to achieve speeds comparable to traditional DRAM, which is crucial for high-performance applications.\n2.  **DDR Compatibility:** The architecture is designed to integrate seamlessly with existing DDR memory interfaces by transmitting and receiving high-speed synchronized data pulses. This reduces adoption barriers and allows for easier integration into current computing systems.\n3.  **Enhanced Reliability and Robustness:** The differential sensing technique inherently provides immunity to common-mode noise, process variations, and temperature fluctuations, leading to more accurate and reliable data retrieval from resistive change elements.\n4.  **Non-Volatility:** As it leverages resistive change elements, the memory retains data even when power is lost, enabling 'persistent memory' capabilities.\n5.  **Power Efficiency:** RRAM generally consumes less power than DRAM, and the efficient sensing mechanism further optimizes energy usage, making it attractive for power-sensitive applications like mobile devices and data centers.","question":"What are the key benefits of Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays?"},{"answer":"Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays differentiates itself from prior art through several key innovations in its approach to RRAM access. Many previous RRAM sensing methods relied on measuring absolute voltage or current levels, which can be slow, prone to noise, and sensitive to manufacturing variations or environmental conditions.\n\nThis patent's distinction lies in its use of a dual-bit line architecture per row and a *differential discharge rate comparison*. Instead of comparing static values, it compares how quickly two parallel paths discharge—one through the memory cell, and one through a precisely calibrated reference element. This dynamic comparison is significantly faster and more robust, as common-mode noise and variations affecting both paths are effectively cancelled out.\n\nFurthermore, the explicit design for high-speed synchronized data pulses makes this technology inherently DDR compatible, a critical feature that many prior RRAM implementations struggled to achieve without significant interface overhead. This comprehensive approach to both sensing mechanism and interface design sets Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays apart as a superior solution for integrating RRAM into high-performance computing.","question":"How is Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays different from prior art?"},{"answer":"The Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent has the potential to profoundly impact a wide array of industries that rely heavily on memory performance and data persistence. Its ability to deliver high-speed, non-volatile, DDR-compatible memory makes it a foundational technology for future computing.\n\n**Data Centers and Cloud Computing:** It can enable faster server boot times, persistent main memory for critical applications, and improved performance for in-memory databases and real-time analytics, leading to more efficient and resilient cloud infrastructure.\n\n**Artificial Intelligence and Machine Learning:** AI accelerators and systems performing complex machine learning tasks will benefit from significantly faster data access and persistent model storage, accelerating training and inference processes.\n\n**High-Performance Computing (HPC):** HPC clusters can achieve higher throughput and reduced latency, crucial for scientific simulations and complex computational problems.\n\n**Edge Computing and IoT:** Devices at the network edge require low-power, high-speed, and persistent memory. This innovation can enable more intelligent, autonomous, and energy-efficient edge devices, from industrial IoT sensors to smart city infrastructure.\n\n**Automotive and Autonomous Vehicles:** Critical systems in autonomous vehicles demand extremely reliable, fast, and persistent memory for real-time decision-making and data logging.\n\n**Consumer Electronics:** While initially targeting enterprise, the technology could eventually lead to consumer devices with instant-on capabilities, longer battery life, and enhanced performance.","question":"What industries will Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays impact?"},{"answer":"The patent Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays (US-9852793) was filed on **June 23, 2016**. The patent was subsequently published, and details regarding its grant would typically follow the publication date.\n\nAccording to the provided data, the publication date for this patent is **December 26, 2017**. The period between filing and publication, and then potentially grant, allows for examination by patent offices and provides public notice of the invention. This timeline indicates that the underlying research and development for this high-speed memory architecture was underway for some time prior to the filing date, reflecting a concerted effort to advance resistive change memory technology.\n\nThese dates are important for understanding the patent's legal lifespan and its position within the timeline of memory technology innovation.","question":"When was Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays filed/granted?"},{"answer":"The commercial applications of Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays are extensive and span multiple high-growth technology sectors. Its core capability—enabling high-speed, DDR-compatible, non-volatile memory—positions it as a foundational technology for next-generation computing systems.\n\n**Persistent Memory Modules (PMMs):** This is a primary application, allowing the creation of memory modules that combine DRAM-like speed with data persistence. These PMMs can be used in servers to eliminate boot times, provide instant recovery from power failures, and accelerate in-memory databases.\n\n**AI/ML Hardware Accelerators:** The technology can be integrated into specialized processors and accelerators for artificial intelligence and machine learning, significantly boosting the performance of training and inference by providing faster, persistent access to large models and datasets.\n\n**Enterprise Storage and Caching:** It can serve as ultra-fast, non-volatile cache memory in enterprise storage systems, dramatically improving I/O performance and reducing latency for critical applications.\n\n**High-Performance Computing (HPC):** HPC systems can leverage this technology for faster checkpointing, reducing the overhead of saving and restoring large computational states, and improving overall system efficiency.\n\n**Embedded Systems and Edge Computing:** For embedded systems and edge devices requiring low power, high reliability, and real-time processing with data persistence, this memory solution offers significant advantages, enabling more intelligent and autonomous devices.","question":"What are the commercial applications of Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays?"},{"answer":"Future developments stemming from the Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent are likely to focus on further optimizing its performance, scalability, and integration into diverse computing environments.\n\nOne key area will be **scaling and density improvements**. As RRAM technology matures, efforts will be made to further miniaturize the resistive change elements and array architecture, increasing memory density while maintaining or improving the high-speed access enabled by this patent. This will make it even more cost-effective and suitable for a broader range of applications.\n\nAnother direction involves **enhanced DDR compatibility and new interface standards**. While already DDR compatible, future iterations may target newer DDR generations (e.g., DDR5, DDR6) or even explore integration with emerging memory interfaces like CXL (Compute Express Link) to maximize bandwidth and minimize latency between the memory and processors.\n\nFurther **optimization of the reference elements and sense amplifiers** could lead to even faster and more power-efficient read operations, potentially pushing RRAM performance even closer to the theoretical limits of dynamic memory. Research into **advanced resistive materials** could also yield RRAM cells with better endurance, faster switching, and more distinct resistance states, further enhancing the benefits of this patented architecture. Ultimately, the long-term vision includes the widespread adoption of this technology in 'universal memory' solutions, fundamentally altering computing architectures.","question":"What are the future developments expected for Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays?"}],"topics":["Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays","resistive change memory","RRAM","DDR compatible memory","high-speed memory","landscape","computing","memory"],"tech_cluster":null},"seo":{"title":"DDR Compatible RRAM - Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays (US-9852793)","description":"Discover the Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays patent for ultra-fast, non-volatile memory. High-speed RRAM with DDR compatibility and differential sensing. Patent US-9852793.","keywords":["Methods for Programming and Accessing Ddr Compatible Resistive Change Element Arrays","resistive change memory","RRAM","DDR compatible memory","high-speed memory","non-volatile memory","memory architecture","patent US-9852793","differential sensing","memory circuit","persistent memory","semiconductor innovation","memory access speed","US-9852793"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852793","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852793","citation_suggestion":"Patentable. \"Methods for programming and accessing DDR compatible resistive change element arrays\" (US-9852793). https://patentable.app/patents/US-9852793","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852793","json":"https://patentable.app/api/llm-context/US-9852793","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:03:45.106Z"}