{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852809","patent":{"patent_number":"US-9852809","title":"Test mode circuit for memory apparatus","assignee":null,"inventors":[],"filing_date":"2015-12-28T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number."},"analysis":{"summary":"The Test Mode Circuit for Memory Apparatus (US-9852809) introduces a significant advancement in the error detection and correction capabilities of semiconductor memory devices. At its core, this innovation addresses the critical challenge of balancing comprehensive error monitoring with efficient system operation, preventing the 'noise' generated by non-critical error signals.\n\nThe patent describes an apparatus that includes at least one memory cell array and a sophisticated control circuit. This control circuit is engineered to receive read data from the memory cells and perform a direct comparison with reference data. The key innovation lies in its intelligent error signal provisioning: an error signal is only generated and provided when the number of detected bit errors is greater than or equal to a predetermined threshold. Conversely, if the number of detected bit errors falls below this predetermined number, the error signal is suppressed.\n\nThis technical approach offers substantial business value. By selectively reporting only significant errors, the invention drastically reduces false positives and unnecessary system interruptions. This leads to improved system uptime, optimized resource utilization (as less processing power is diverted to minor error handling), and clearer, more actionable diagnostic information for maintenance and troubleshooting. It effectively allows memory systems to 'ignore' correctable, benign errors, focusing resources on critical integrity issues.\n\nSuch a technology holds immense market opportunity across various high-reliability sectors. Industries like cloud computing, automotive (especially autonomous vehicles), medical devices, and enterprise data storage, which demand continuous operation and pristine data integrity, stand to benefit significantly. The Test Mode Circuit for Memory Apparatus enables the creation of more robust, resilient, and efficient memory architectures, promising enhanced performance and reduced operational costs for next-generation semiconductor devices.","layman_explanation":"### 1. What Problem Does This Solve?\nImagine you're running a massive online store, and your servers are constantly processing millions of customer orders, product updates, and inventory changes. This data is stored in what we call 'memory.' In these complex digital environments, sometimes tiny, fleeting errors can occur in memory. These aren't usually catastrophic, but traditional systems often treat every single one like a major emergency, triggering alerts, slowing down operations, or even causing temporary shutdowns.\n\nThis 'over-reporting' of minor errors creates significant business problems. It leads to what we call 'diagnostic fatigue' – where IT teams are flooded with so many alerts that they can't easily distinguish a critical problem from a trivial one. It also wastes valuable computing resources, as the system has to process and log every minor error, impacting overall performance and adding to operational costs. Existing solutions often either miss subtle errors or generate too much noise, neither of which is ideal for a high-stakes business environment.\n\n### 2. How Does It Work?\nThis patent, the **Test Mode Circuit for Memory Apparatus**, introduces a much smarter way to handle these memory errors. Think of it like a highly intelligent quality control inspector for your data. Instead of shouting 'Problem!' every time a single item is slightly out of place on an assembly line, this inspector has a refined judgment.\n\nHere's the concept: When data is read from memory, this special circuit acts as a gatekeeper. It compares the data it just read with what the data *should* look like (its 'reference data'). If it finds a few small discrepancies – let's say, less than five tiny errors in a large batch of data – and it knows these are easily fixable or not critical, it simply corrects them silently. It doesn't send out an alarm.\n\nHowever, if the number of errors it finds crosses a certain 'magic threshold' – say, five or more significant errors – then it *does* raise a flag. It's like the inspector only calls the manager when there's a serious flaw that could impact the product's function or safety, not for every tiny scratch that can be buffed out. This selective reporting ensures that only genuine, potentially impactful issues are escalated, while the system continues to run smoothly through minor, self-correcting events.\n\n### 3. Why Does This Matter?\nThis innovation matters immensely for businesses. First, it directly translates into **improved system uptime and reliability**. Your servers, cloud infrastructure, or embedded devices will experience fewer unnecessary interruptions, meaning continuous service for your customers and employees. This directly impacts revenue streams and customer satisfaction.\n\nSecond, it leads to **more efficient resource utilization and lower operational costs**. By reducing the 'noise' of minor error alerts, your IT teams can focus their expertise on truly critical issues, saving time and labor. The computing resources that were once spent processing trivial errors can now be dedicated to core business functions, improving overall performance and reducing energy consumption.\n\nThird, it provides a **competitive advantage**. Companies that integrate this technology can offer more robust and dependable products, appealing to clients in industries where data integrity and continuous operation are non-negotiable, such as financial services, healthcare, and automotive. It positions a company as a leader in intelligent, fault-tolerant hardware.\n\n### 4. What's Next?\nThis technology paves the way for even more resilient and 'self-healing' computing systems. We could see applications in next-generation autonomous vehicles, where memory integrity is literally a matter of life and death, or in hyper-scale data centers aiming for 'nine nines' (99.9999999%) uptime. As AI and IoT proliferate, the demand for intelligent, reliable memory will only grow. This patent represents a foundational step towards memory systems that are not just error-detecting, but *error-wise*, making them an even more indispensable component of our digital future.","technical_analysis":"The Test Mode Circuit for Memory Apparatus (US-9852809) addresses a fundamental challenge in semiconductor memory design: the efficient and intelligent management of bit errors. As memory densities increase and operating voltages decrease, the susceptibility to soft errors and transient faults becomes more pronounced. This patent introduces a sophisticated control circuit that significantly refines the traditional error detection and reporting mechanisms.\n\n**Technical Architecture and Components:**\nThe core apparatus, as described, comprises:\n1.  **Memory Cell Array:** A standard array of memory cells (e.g., DRAM, NAND flash) from which data is read.\n2.  **Control Circuit:** The central innovation, responsible for intelligent error processing. This circuit can be conceptualized as having several logical blocks:\n    *   **Data Receiver:** Interfaces with the memory cell array to acquire read data.\n    *   **Reference Data Source:** Provides expected or known good data for comparison. This could be stored internally, generated on-the-fly, or derived from error-correcting code (ECC) parity bits.\n    *   **Comparator Logic:** Performs a bit-by-bit or block-wise comparison between the received read data and the reference data, identifying discrepancies (bit errors).\n    *   **Error Counter:** Aggregates the number of detected bit errors within a specific read operation or data block.\n    *   **Threshold Logic:** A crucial element that compares the accumulated error count from the Error Counter against a *predetermined number*. This threshold can be static (hardcoded) or dynamic (programmable via a register).\n    *   **Error Signal Generator/Suppressor:** Based on the Threshold Logic's output, this unit either asserts an error signal (e.g., an interrupt, a flag in a status register) or explicitly suppresses it.\n\n**Implementation Details and Algorithm Specifics:**\nThe operational flow involves:\n1.  **Data Read:** A read operation is initiated, and data is fetched from the memory cell array.\n2.  **Comparison:** The control circuit's comparator logic immediately compares the read data with its corresponding reference data. This comparison identifies individual bit errors.\n3.  **Error Counting:** The detected bit errors are tallied by the error counter. This count typically pertains to a specific data word, block, or a defined window of operation.\n4.  **Threshold Evaluation:** The accumulated error count is then fed to the threshold logic. This logic performs a simple conditional check: `if (error_count >= predetermined_number) { assert_error_signal(); } else { suppress_error_signal(); }`.\n5.  **Signal Provisioning:** If the condition is met, a system-level error signal is provided. If not, no error signal is generated, preventing unnecessary interruptions.\n\nThis mechanism directly complements existing error correction techniques, such as ECC. For instance, if an ECC scheme can correct up to 'N' bit errors, the 'predetermined number' threshold could be set to 'N+1'. This ensures that only errors that exceed the ECC's capabilities (i.e., uncorrectable errors or those indicating a more severe fault) trigger a system alert. Minor, correctable errors are handled silently by the ECC, and their detection is not escalated to higher system layers.\n\n**Integration Patterns and Performance Characteristics:**\nIntegration of this technology would typically occur at the memory controller level or within the memory module itself. It can be implemented as a dedicated hardware block (ASIC) or as part of an FPGA/SoC design. Performance benefits include reduced interrupt latency and overhead, as the CPU or main controller is not constantly interrupted by benign error events. This leads to more deterministic system behavior and improved throughput in data-intensive applications. Power consumption can also be optimized by reducing the frequency of error handling routines.\n\n**Code-Level Implications:**\nFrom a software perspective, this invention simplifies error handling routines. Operating systems and applications would encounter fewer, but more critical, error signals. This allows for more streamlined exception handling, focusing on recovery from severe data corruption rather than trivial, self-correcting issues. Firmware and drivers could be designed to react only to genuine threats, leading to more robust and efficient software stacks. The Test Mode Circuit for Memory Apparatus fundamentally shifts the burden of initial error triage from the software layer to a dedicated, intelligent hardware circuit, thereby enhancing overall system resilience and performance.","business_analysis":"The **Test Mode Circuit for Memory Apparatus** (US-9852809) represents a strategic innovation with significant commercial implications for the semiconductor and electronics industries. By intelligently managing error signals in memory apparatuses, this patent addresses a critical pain point: the trade-off between comprehensive error detection and efficient system operation. This has a direct impact on product reliability, operational costs, and market competitiveness.\n\n**Market Opportunity Size:**\nThe market for semiconductor memory is vast and continuously expanding, driven by explosive growth in data centers, AI/ML, IoT, autonomous vehicles, and high-performance computing. Every device relying on memory, from consumer smartphones to industrial servers, stands to benefit from enhanced reliability. The global memory market, valued in hundreds of billions of dollars, presents a massive TAM (Total Addressable Market) for technologies that improve memory integrity and efficiency. Solutions that reduce system downtime and maintenance costs resonate strongly across all segments.\n\n**Competitive Advantages:**\nThis patent offers several distinct competitive advantages:\n1.  **Superior Reliability:** By reducing false positives and unnecessary error signals, products incorporating this technology can boast higher actual uptime and data integrity compared to those relying on less sophisticated error management.\n2.  **Optimized Performance:** Less CPU overhead for error handling translates into more available processing power for core tasks, offering a performance edge in demanding applications.\n3.  **Reduced Total Cost of Ownership (TCO):** Fewer system interruptions, extended hardware lifespan due to optimized error handling, and more efficient diagnostics contribute to lower operational and maintenance costs for end-users and enterprises.\n4.  **Differentiation in High-Reliability Markets:** Manufacturers can position their memory modules or devices as 'enterprise-grade' or 'safety-critical' by leveraging the intelligent error management capabilities of this invention.\n\n**Revenue Potential and Business Models:**\nRevenue potential can be realized through various business models:\n*   **Licensing:** Semiconductor IP companies or memory manufacturers can license the patent for integration into their memory controllers, DRAM modules, or flash storage devices.\n*   **Product Integration:** Companies that manufacture memory chips or modules can integrate this technology directly, offering premium products with enhanced reliability features.\n*   **System-Level Solutions:** OEMs building complex systems (e.g., servers, automotive ECUs) can specify or develop memory subsystems that incorporate this intelligent error management, differentiating their end products.\n\n**Strategic Positioning:**\nCompanies adopting this technology can strategically position themselves as leaders in 'resilient computing' or 'intelligent hardware.' This aligns with broader industry trends emphasizing fault tolerance, self-healing systems, and edge computing reliability. The Test Mode Circuit for Memory Apparatus can become a standard feature in next-generation memory standards or a key differentiator in high-value market segments.\n\n**ROI Projections:**\nWhile specific ROI will vary, the benefits are clear:\n*   **For Memory Manufacturers:** Increased market share due to superior product reliability, premium pricing opportunities, and reduced warranty claims.\n*   **For System Integrators/OEMs:** Enhanced brand reputation for reliability, reduced customer support costs related to memory errors, and competitive advantage in performance-critical applications.\n*   **For End-Users/Enterprises:** Significant savings from reduced downtime, improved data availability, and lower IT operational expenses. For a data center, even a small percentage increase in uptime translates to millions in savings. The Test Mode Circuit for Memory Apparatus promises a strong return on investment by mitigating one of the most persistent issues in digital infrastructure.","faqs":[{"answer":"The Test Mode Circuit for Memory Apparatus is an innovative patent (US-9852809) that describes an advanced apparatus for error detection and correction within semiconductor memory devices. At its core, this invention introduces a sophisticated control circuit designed to intelligently manage error signals, rather than simply reporting every detected error.\n\nSpecifically, the apparatus includes at least one memory cell array and a control circuit. This control circuit receives read data from the memory cells and compares it with reference data. The key differentiating feature is its selective error signaling mechanism.\n\nThis technology ensures that only significant errors, those that meet or exceed a predetermined threshold, trigger an error signal. Conversely, minor errors that fall below this threshold are suppressed. This approach prevents 'diagnostic fatigue' and unnecessary system interruptions, leading to more robust and efficient memory operation. It represents a significant step forward in optimizing memory reliability and performance.","question":"What is Test Mode Circuit for Memory Apparatus?"},{"answer":"The Test Mode Circuit for Memory Apparatus operates through a clever, multi-step process orchestrated by its control circuit. First, when data is read from the memory cell array, the control circuit receives this raw read data. Second, it performs a crucial comparison: it evaluates the received read data against known reference data, identifying any discrepancies or 'bit errors.'\n\nThird, and most importantly, the control circuit applies a threshold-based decision-making process. It counts the number of detected bit errors. If this count is greater than or equal to a pre-defined 'predetermined number,' it then provides an error signal to the rest of the system, indicating a potentially critical issue.\n\nHowever, if the number of detected bit errors is less than this predetermined number, the control circuit *suppresses* the error signal. This means minor, often correctable errors (which might otherwise be handled silently by Error-Correcting Codes or ECC) do not generate unnecessary alerts, thereby reducing system overhead and improving overall efficiency. This intelligent filtering is central to how the Test Mode Circuit for Memory Apparatus enhances memory reliability. Keywords: control circuit, read data, reference data, bit errors, predetermined number, error signal suppression.","question":"How does Test Mode Circuit for Memory Apparatus work?"},{"answer":"The Test Mode Circuit for Memory Apparatus primarily solves the problem of inefficient and overly verbose error reporting in semiconductor memory systems. In traditional approaches, every detected bit error, regardless of its severity or whether it was easily correctable by underlying mechanisms like ECC, would often trigger an error signal. This leads to several issues:\n\n1.  **Diagnostic Fatigue:** System administrators and automated systems are inundated with alerts for minor, non-critical errors, making it difficult to distinguish genuine threats from benign events.\n2.  **Performance Degradation:** Frequent error signals lead to CPU interrupts and memory controller overhead, diverting valuable processing resources and increasing latency.\n3.  **Reduced System Uptime:** Unnecessary alerts can trigger unwarranted system reboots or service interruptions, impacting operational continuity and profitability.\n\nThis invention addresses these challenges by intelligently filtering error signals, ensuring that only significant, actionable errors are reported. This optimizes system resources, improves diagnostic clarity, and boosts overall system stability and uptime. Keywords: inefficient error reporting, diagnostic fatigue, system overhead, performance degradation, system uptime.","question":"What problem does Test Mode Circuit for Memory Apparatus solve?"},{"answer":"The patent US-9852809, titled Test Mode Circuit for Memory Apparatus, lists the inventors as [Inventors' Names - *not provided in prompt, so will leave blank or state as not provided*]. The assignee for this patent is [Assignee Name - *not provided in prompt, so will leave blank or state as not provided*].\n\nWhile the specific individuals and company behind this innovation are not detailed in the provided abstract, the invention itself focuses on apparatuses for error detection and correction for semiconductor devices. The development of such sophisticated error management systems typically involves teams of highly skilled engineers and researchers specializing in semiconductor design, memory architecture, and digital logic. Their collective expertise contributes to creating solutions that enhance the reliability and efficiency of memory components, a critical area in modern computing. Keywords: inventors, assignee, semiconductor design, memory architecture, digital logic.","question":"Who invented Test Mode Circuit for Memory Apparatus?"},{"answer":"The Test Mode Circuit for Memory Apparatus offers several compelling benefits that significantly enhance the performance and reliability of semiconductor memory systems:\n\n1.  **Improved System Uptime and Stability:** By suppressing signals for minor, correctable errors, the system experiences fewer unnecessary interruptions, leading to more consistent operation and higher availability.\n2.  **Optimized Resource Utilization:** Reduced frequency of error signals means less processing overhead for the CPU or memory controller, freeing up valuable computational resources for core tasks.\n3.  **Clearer Diagnostics:** IT professionals receive cleaner, more actionable error logs, allowing them to quickly identify and address genuine threats without being overwhelmed by a flood of minor alerts.\n4.  **Enhanced Data Integrity:** The focus on critical errors ensures that serious threats to data integrity are promptly addressed, while benign errors are handled efficiently in the background.\n5.  **Reduced Total Cost of Ownership (TCO):** Lower maintenance costs, extended hardware lifespan due to optimized error handling, and improved operational efficiency contribute to significant long-term savings for enterprises. This technology fundamentally makes memory systems smarter, more resilient, and more efficient. Keywords: system uptime, resource optimization, data integrity, clearer diagnostics, TCO, memory reliability.","question":"What are the key benefits of Test Mode Circuit for Memory Apparatus?"},{"answer":"The Test Mode Circuit for Memory Apparatus distinguishes itself from prior art through its intelligent, threshold-based error signaling mechanism, moving beyond simple exhaustive error reporting. Prior art solutions, such as basic parity checking or even advanced ECC systems, typically generate an error signal for nearly every detected bit error, regardless of its severity or if it's already been corrected.\n\nThis invention's key difference lies in its control circuit's ability to count detected bit errors and compare this count against a 'predetermined number.' Unlike prior art, it actively *suppresses* error signals if the error count is below this threshold, and *only* provides an error signal if the count meets or exceeds it. This means minor, correctable errors are handled silently, without burdening the main system with unnecessary alerts.\n\nThis selective reporting prevents 'diagnostic fatigue' and optimizes system performance by reducing CPU interrupts and error handling overhead. Prior art tends to be 'noisy' and less efficient in its error management, whereas the Test Mode Circuit for Memory Apparatus offers a more refined, intelligent, and resource-efficient approach to maintaining memory integrity. Keywords: prior art, intelligent error signaling, threshold-based, error suppression, diagnostic noise, ECC, memory efficiency.","question":"How is Test Mode Circuit for Memory Apparatus different from prior art?"},{"answer":"The Test Mode Circuit for Memory Apparatus is poised to significantly impact a wide array of industries that rely heavily on high-performance and highly reliable semiconductor memory. Its ability to intelligently manage errors makes it invaluable across various sectors:\n\n1.  **Cloud Computing and Data Centers:** Critical for maintaining high uptime, reducing operational costs, and ensuring data integrity across vast server infrastructures.\n2.  **Automotive (Especially Autonomous Vehicles):** In safety-critical applications, precise and intelligent error reporting without false positives is paramount for reliable operation and decision-making.\n3.  **Artificial Intelligence and Machine Learning:** Essential for ensuring continuous, error-free data streams during model training and real-time inference, where interruptions can be costly.\n4.  **Enterprise Storage:** For businesses managing large volumes of sensitive data, this technology ensures robust and trustworthy storage systems.\n5.  **Medical Devices:** In devices where reliability is literally a matter of life and death, intelligent error management enhances system dependability.\n6.  **Embedded Systems and IoT:** For devices operating in remote or harsh environments, self-managing and robust memory systems are crucial for long-term, low-maintenance operation. The innovation's core benefit of enhanced reliability and efficiency is universally valuable where memory is a key component. Keywords: cloud computing, data centers, autonomous vehicles, AI/ML, enterprise storage, medical devices, IoT, semiconductor industry.","question":"What industries will Test Mode Circuit for Memory Apparatus impact?"},{"answer":"The Test Mode Circuit for Memory Apparatus patent, identified as US-9852809, has specific dates associated with its lifecycle:\n\n*   **Filing Date:** The patent application for this invention was filed on **December 28, 2015**.\n*   **Publication Date:** The patent was subsequently published, meaning it was officially granted and made public, on **December 26, 2017**.\n\nThese dates mark important milestones in the intellectual property protection of this innovation. The period between the filing and publication dates allows for examination by patent offices, during which the claims are reviewed against existing prior art to ensure novelty and non-obviousness. The granting of the patent signifies that the claims of the Test Mode Circuit for Memory Apparatus were deemed inventive and enforceable, providing legal protection for its unique approach to memory error detection and correction. Keywords: filing date, publication date, patent grant, US-9852809, intellectual property.","question":"When was Test Mode Circuit for Memory Apparatus filed/granted?"},{"answer":"The commercial applications of the Test Mode Circuit for Memory Apparatus are extensive, spanning any sector that demands high-reliability and efficient semiconductor memory. Its core benefit of intelligent error management translates directly into tangible business value.\n\nKey commercial applications include:\n\n1.  **High-End Servers and Workstations:** Enhancing the stability and uptime of critical computing infrastructure in data centers, cloud platforms, and enterprise networks.\n2.  **Solid-State Drives (SSDs) and Storage Devices:** Improving the longevity and data integrity of high-performance storage solutions, crucial for both consumer and enterprise markets.\n3.  **Automotive Electronics:** Integrating into Electronic Control Units (ECUs) and advanced driver-assistance systems (ADAS) to ensure fault-tolerant operation in vehicles.\n4.  **Networking Equipment:** Boosting the reliability of routers, switches, and other network infrastructure components that handle continuous data traffic.\n5.  **Industrial Control Systems:** Providing robust memory solutions for critical industrial automation and control processes where downtime is costly.\n6.  **Consumer Electronics:** Contributing to more stable and reliable performance in smartphones, laptops, and other devices, reducing crashes and improving user experience. The Test Mode Circuit for Memory Apparatus enables manufacturers to offer premium, more dependable products across these diverse markets. Keywords: commercial applications, SSDs, servers, automotive, networking, industrial control, consumer electronics.","question":"What are the commercial applications of Test Mode Circuit for Memory Apparatus?"},{"answer":"The Test Mode Circuit for Memory Apparatus lays a strong foundation for several exciting future developments in memory reliability and fault tolerance. Building upon its intelligent error filtering, we can anticipate advancements that will make memory systems even more robust and autonomous:\n\n1.  **Adaptive Thresholds:** Future iterations may feature dynamically adjustable 'predetermined numbers' (error thresholds). These could adapt in real-time based on environmental factors (temperature, voltage), memory wear-out, or even the criticality of the data being stored, allowing for more nuanced error management.\n2.  **Predictive Error Management:** Integration with machine learning algorithms could enable the system to not only detect and filter errors but also predict potential memory failures before they occur. This would allow for proactive maintenance, such as remapping faulty memory blocks or scheduling replacements, minimizing downtime.\n3.  **Self-Healing Architectures:** The technology could evolve to initiate autonomous recovery actions beyond simply correcting errors. This might include reconfiguring memory arrays or isolating degraded sections without requiring human intervention.\n4.  **Context-Aware Reliability:** Memory systems could become aware of the importance of specific data, applying stricter error thresholds for mission-critical information versus temporary data. This would lead to highly optimized and resilient memory subsystems. The Test Mode Circuit for Memory Apparatus is a critical step towards truly self-aware and fault-tolerant memory, essential for the next generation of AI, IoT, and high-performance computing. Keywords: future developments, adaptive thresholds, predictive error management, self-healing, context-aware reliability, AI, IoT.","question":"What are the future developments expected for Test Mode Circuit for Memory Apparatus?"}],"topics":["Test Mode Circuit for Memory Apparatus","memory error detection","semiconductor reliability","error correction","memory apparatus","increasing","demand","performance"],"tech_cluster":null},"seo":{"title":"Test Mode Circuit for Memory Apparatus - US-9852809 Patent","description":"Discover the Test Mode Circuit for Memory Apparatus patent (US-9852809) for intelligent error detection in memory. Boost reliability, optimize performance, and get clearer diagnostics.","keywords":["Test Mode Circuit for Memory Apparatus","memory error detection","semiconductor reliability","error correction","memory apparatus","intelligent error signaling","fault tolerance","US-9852809","patent analysis","data integrity","memory circuit","bit error detection","control circuit","semiconductor device"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852809","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852809","citation_suggestion":"Patentable. \"Test mode circuit for memory apparatus\" (US-9852809). https://patentable.app/patents/US-9852809","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852809","json":"https://patentable.app/api/llm-context/US-9852809","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:04:27.533Z"}