{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852810","patent":{"patent_number":"US-9852810","title":"Optimizing fuseROM usage for memory repair","assignee":null,"inventors":[],"filing_date":"2015-06-08T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register have a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain."},"analysis":{"summary":"The patent \"Optimizing Fuserom Usage for Memory Repair\" introduces a highly efficient memory repair system for integrated circuits (ICs). At its core, this innovation addresses the significant challenge of managing defective memory blocks in increasingly complex semiconductor designs without incurring excessive overhead in terms of chip area and power consumption.\n\nThe central problem it solves is the traditional inefficiency of fuseROM (Fuse Read-Only Memory) allocation. Conventional methods often reserve fuseROM space for every potential memory repair, regardless of whether a block is actually defective. This leads to substantial waste and increased manufacturing costs. This patent provides a sophisticated solution to this dilemma.\n\nTechnically, the system comprises multiple memory wrappers, each containing a memory block, a fuse register, and a bypass register. A crucial component is the 'memory bypass chain,' which links all bypass registers to a central fuseROM controller. This chain allows for a rapid, low-overhead scan to identify defective memory wrappers using compact 'bypass data.' Once a defective wrapper is flagged, the fuseROM controller dynamically reconfigures a 'memory data chain' to specifically access the fuse registers of *only* those identified faulty blocks. This selective data loading mechanism is the cornerstone of its efficiency.\n\nFrom a business perspective, Optimizing Fuserom Usage for Memory Repair offers substantial value. It enables semiconductor manufacturers to achieve higher yields by more effectively managing memory defects. The reduction in required fuseROM translates directly to smaller die sizes and lower production costs. Furthermore, it enhances the scalability of memory repair solutions, allowing for the integration of larger and denser memory arrays in future IC designs without corresponding increases in overhead. This positions the technology as a key enabler for advanced, cost-effective, and highly reliable ICs across various industries, from consumer electronics to high-performance computing. The market opportunity lies in providing a superior, more economical method for ensuring the integrity of on-chip memory.","layman_explanation":"### What Problem Does This Solve?\nImagine you're running a massive factory that produces millions of identical products, like computer chips. Each chip has many small, critical components called 'memory blocks.' Sometimes, during manufacturing, a few of these memory blocks might have tiny flaws. To ensure the final product works perfectly, these flaws need to be fixed or 'repaired.'\n\nThe traditional way of repairing memory in chips is like keeping a huge, detailed instruction manual for *every single component* in every product, just in case it breaks. Even if 99% of components are perfectly fine, you still have to dedicate valuable space on the chip (called 'fuseROM') to store potential repair instructions for all of them. This leads to bigger, more expensive chips, and it takes a long time to sort through all those manuals to find the few that are actually needed for repair. The problem is inefficiency and excessive overhead for a necessary function.\n\n### How Does It Work?\n\"Optimizing Fuserom Usage for Memory Repair\" introduces a much smarter, more efficient approach. Think of it like a modern, digital inventory system for your factory.\n\nInstead of a full manual for every component, each memory block now has a tiny, quick-check sensor (a 'bypass register' with 'bypass data'). This sensor simply tells you, 'Is this specific memory block okay, or does it have a problem?' All these sensors are linked together in a 'memory bypass chain,' which is like a rapid scanning system.\n\nFirst, a central control unit (the 'fuseROM controller') quickly scans all these quick-check sensors. It instantly gets a report: 'Component A has a problem, Component G has a problem, but all others are fine.' This is much faster than reading full manuals for everything.\n\nOnce the control unit knows *exactly* which few components are faulty, it then, and *only then*, accesses the detailed repair instructions (from 'fuse registers') specifically for Component A and Component G. It doesn't waste time or resources looking at the instructions for the perfectly fine components. This dynamic, targeted approach is the core of this invention's efficiency.\n\n### Why Does This Matter?\nThis innovation matters significantly for several business reasons:\n\n*   **Cost Reduction:** By using fuseROM much more efficiently, chip manufacturers can design smaller chips. Smaller chips mean more chips can be produced on a single silicon wafer, dramatically reducing the per-chip manufacturing cost. This directly impacts profit margins and makes products more competitive.\n*   **Improved Product Quality and Reliability:** The system ensures that memory defects are repaired effectively, leading to more reliable chips and, consequently, more dependable electronic devices. This reduces warranty claims, enhances customer satisfaction, and builds brand trust.\n*   **Scalability for Future Products:** As devices become more powerful, they need more memory. Traditional repair methods would become prohibitively expensive and space-consuming. This technology provides a scalable solution, allowing companies to integrate larger and denser memory arrays into future products without the usual cost penalties, enabling continued innovation in areas like AI, IoT, and high-performance computing.\n*   **Faster Time-to-Market:** More efficient repair processes can also streamline testing and debugging phases during manufacturing, potentially accelerating product development cycles.\n\n### What's Next?\nThis patent lays a foundational block for the next generation of integrated circuits. We can expect to see this approach integrated into a wide range of semiconductor products, from consumer electronics like smartphones and smart home devices to industrial control systems and automotive electronics. The market adoption timeline will likely accelerate as manufacturers seek to gain competitive advantages in cost and reliability. For investors, this represents an opportunity in companies that either license this core technology or are early adopters in their own product lines, as it promises a tangible return on investment through efficiency gains and market leadership.","technical_analysis":"The patent \"Optimizing Fuserom Usage for Memory Repair\" delineates a sophisticated memory repair system for integrated circuits (ICs) that innovatively addresses the challenges of fuseROM utilization and memory defect management. This technical analysis will delve into the architectural components, operational specifics, and the underlying algorithms that contribute to the efficiency and scalability of this invention.\n\n**Technical Architecture and Components:**\nThe core architecture revolves around a plurality of 'memory wrappers,' each acting as a self-contained unit for a memory block. Each wrapper is equipped with:\n1.  **Memory Block:** The actual memory array that may contain defects.\n2.  **Fuse Register:** A non-volatile register associated with the memory block, designed to store detailed repair data (e.g., redundant row/column addresses) if the block is found to be defective.\n3.  **Bypass Register:** A smaller, non-volatile register that stores 'bypass data.' This data is a compact indicator (e.g., a single bit or a few bits) signaling whether its corresponding memory wrapper is defective or not.\n\nA central **FuseROM Controller** is coupled to all these memory wrappers, acting as the orchestrator of the repair process. The controller interacts with the wrappers through two distinct, yet interconnected, data chains:\n1.  **Memory Bypass Chain:** This chain serially or parallelly links the bypass registers across all memory wrappers to the fuseROM controller. Its primary function is to quickly propagate the bypass data from all wrappers to the controller.\n2.  **Memory Data Chain:** This chain links the fuse registers in the memory wrappers to the fuseROM controller. Crucially, this chain is designed for re-configuration.\n\n**Implementation Details and Algorithm Specifics:**\nThe operational flow of this system is a two-phase process, designed for optimal efficiency:\n\n**Phase 1: Defective Wrapper Identification (Bypass Data Loading):**\n*   The fuseROM controller initiates a read operation on the memory bypass chain.\n*   Bypass data from all memory wrappers is loaded into the fuseROM controller. This data is significantly smaller than full repair data, allowing for a rapid scan of the entire memory system.\n*   The fuseROM controller then processes this bypass data to create a list or map of 'defective memory wrappers.' This list indicates precisely which memory blocks require detailed repair.\n\n**Phase 2: Targeted Repair Data Loading (Fuse Register Access):**\n*   Based on the identified defective memory wrappers, the fuseROM controller dynamically re-configures the memory data chain. This re-configuration involves activating or routing the data path *only* to the fuse registers of the defective wrappers.\n*   The fuseROM controller then reads the detailed repair data from the fuse registers of these selected defective memory wrappers.\n*   This repair data is then used to configure redundant memory elements within the respective memory blocks, effectively repairing the defects.\n\nThe algorithm's efficiency stems from avoiding a full scan and load of fuse register data for every memory wrapper. Instead, it uses a low-overhead preliminary scan to pinpoint problematic areas, followed by a surgical, targeted data load. This significantly reduces overall fuseROM access time and power consumption during the repair process.\n\n**Integration Patterns and Performance Characteristics:**\nThis architecture is highly amenable to integration into complex System-on-Chips (SoCs). The memory wrappers can be instantiated as reusable IP blocks, simplifying design. The fuseROM controller would be a dedicated logic block, potentially with a small amount of embedded non-volatile memory for its own configuration or critical parameters. The dynamic re-configuration of the memory data chain implies sophisticated multiplexing and address decoding logic, driven by the fuseROM controller's output.\n\nPerformance-wise, the system offers faster repair initiation due to the quick bypass scan. The reduction in total fuseROM reads translates to lower power consumption during test and repair cycles. The area overhead for the bypass registers is minimal compared to the savings from reducing the overall fuseROM footprint. This innovation particularly shines in scenarios with high memory instance counts but a relatively low statistical defect rate.\n\n**Code-Level Implications:**\nFor hardware description languages (HDLs) like Verilog or VHDL, the memory wrappers would be modular entities. The fuseROM controller would implement state machines and combinatorial logic to manage the bypass chain, decode bypass data, and control the re-configuration of the memory data chain. The bypass and fuse registers would be modeled as non-volatile storage elements, with appropriate read/write interfaces. Simulation and verification would focus on ensuring correct identification of defective wrappers and accurate, targeted loading of repair data, as well as timing closure for the data chains. This system provides a robust and efficient framework for enhancing the reliability of modern ICs.","business_analysis":"The patent \"Optimizing Fuserom Usage for Memory Repair\" represents a significant advancement in semiconductor technology, with profound implications for the business landscape of integrated circuit (IC) manufacturing. This innovation directly addresses critical industry pain points, unlocking substantial market opportunities and competitive advantages for adopters.\n\n**Market Opportunity Size:**\nThe global semiconductor memory market, a multi-billion dollar industry, is constantly pushing for higher densities, lower power, and greater reliability. Every IC, from microcontrollers to high-performance processors, incorporates embedded memory, making efficient memory repair a universal need. The market for memory repair solutions, while often embedded, is valued in the billions, driven by the need to salvage chips that would otherwise be discarded due to minor defects. By reducing the cost and overhead of repair, this patent expands the addressable market for complex, high-yield ICs. Industries like mobile computing, IoT, automotive electronics, and data centers, which demand highly reliable and compact memory solutions, stand to benefit immensely. The ability to increase yields by even a few percentage points across millions of units translates to hundreds of millions in revenue.\n\n**Competitive Advantages:**\nCompanies that implement the technology described in Optimizing Fuserom Usage for Memory Repair will gain a distinct competitive edge through several avenues:\n1.  **Cost Reduction:** By significantly reducing the required fuseROM area, manufacturers can produce smaller dies, leading to more chips per wafer and dramatically lower per-unit manufacturing costs. This directly impacts profit margins and pricing competitiveness.\n2.  **Improved Yields:** More efficient and effective memory repair means a higher percentage of manufactured chips will meet quality standards, reducing waste and improving overall production yield.\n3.  **Enhanced Product Performance & Reliability:** Devices incorporating this technology will offer superior memory reliability, translating to fewer field failures, better customer satisfaction, and stronger brand reputation. The faster repair process can also contribute to quicker device boot-up times or more responsive error handling.\n4.  **Scalability & Future-Proofing:** As memory densities continue to grow, traditional repair methods become increasingly cumbersome. This innovation provides a scalable solution, enabling companies to integrate larger memory arrays without prohibitive overheads, thus future-proofing their IC designs for next-generation products.\n\n**Revenue Potential and Business Models:**\nThe revenue potential for this patent is primarily indirect, through the value it adds to semiconductor products. For an assignee, licensing this technology to major IC manufacturers could generate substantial royalties. Alternatively, a company directly implementing this innovation in its own product lines would see increased profitability through cost savings and market share gains due to superior product offerings. Potential business models include:\n*   **Direct IP Licensing:** Offering the architectural IP to chip designers and foundries.\n*   **Embedded in Foundry Services:** Foundries could offer processes optimized for this repair mechanism as a value-added service.\n*   **Product Differentiation:** Semiconductor companies using this in their proprietary chips can market 'enhanced reliability' and 'lower power' as key differentiators.\n\n**Strategic Positioning:**\nThis patent strategically positions a company at the forefront of IC reliability and cost optimization. It moves beyond incremental improvements in manufacturing processes to a fundamental architectural enhancement in defect management. This allows companies to pursue aggressive integration strategies for memory-rich SoCs, enabling new product categories and capabilities that might have been economically unfeasible with older repair methodologies.\n\n**ROI Projections:**\nWhile specific ROI depends on implementation scale and market factors, the reduction in fuseROM area alone can yield significant returns. For a typical high-volume IC, a 10-30% reduction in die area from fuseROM optimization could translate to millions of dollars in savings per wafer run, quickly recouping any R&D investment. Coupled with improved yields and enhanced market perception, the ROI is compelling, making Optimizing Fuserom Usage for Memory Repair an attractive investment for semiconductor giants and a powerful tool for startups aiming to disrupt the market with more efficient chip designs.","faqs":[{"answer":"Optimizing Fuserom Usage for Memory Repair is a patented memory repair system designed for integrated circuits (ICs). This innovative technology focuses on making the process of fixing defective memory blocks within a chip much more efficient and cost-effective. It achieves this by intelligently managing the use of fuseROM (Fuse Read-Only Memory), which is a special type of non-volatile memory used to store repair instructions.\n\nInstead of the traditional method of allocating fuseROM for every potential memory repair, this patent introduces a dynamic, two-stage approach. It first quickly identifies only the actual defective memory regions and then selectively loads the detailed repair data for those specific regions. This significantly reduces the overall fuseROM footprint and streamlines the repair process.\n\nEssentially, this invention helps chips fix themselves smarter, leading to more reliable devices, lower manufacturing costs, and improved scalability for future, more complex chip designs. It's a key advancement in semiconductor reliability engineering.","question":"What is Optimizing Fuserom Usage for Memory Repair?"},{"answer":"The core of how Optimizing Fuserom Usage for Memory Repair works lies in its two-phase, intelligent data handling. The system integrates multiple 'memory wrappers,' each containing a memory block, a fuse register, and a bypass register.\n\nIn the first phase, a 'memory bypass chain' links all bypass registers to a central 'fuseROM controller.' Each bypass register holds compact 'bypass data' that quickly indicates if its memory wrapper is defective. The fuseROM controller rapidly scans this bypass chain to identify all faulty memory blocks with minimal overhead.\n\nIn the second phase, once defective wrappers are identified, the fuseROM controller dynamically 're-configures' a 'memory data chain.' This re-configuration ensures that detailed repair information from the fuse registers is loaded *only* from the set of defective memory wrappers. This targeted data retrieval avoids unnecessary fuseROM access, saving chip area, power, and time. It's like a rapid diagnostic test followed by a precise surgical repair.","question":"How does Optimizing Fuserom Usage for Memory Repair work?"},{"answer":"Optimizing Fuserom Usage for Memory Repair solves the significant problem of inefficient fuseROM utilization in integrated circuit (IC) memory repair. In traditional systems, fuseROM is often statically allocated for every memory block, regardless of whether it's defective. This leads to several issues:\n\nFirstly, it results in excessive chip area overhead, as large amounts of fuseROM are reserved but often unused, increasing manufacturing costs. Secondly, it contributes to higher power consumption during memory testing and initialization phases due to the need to scan through extensive, often irrelevant, repair data. Thirdly, it creates scalability limitations, making it challenging to integrate larger and denser memory arrays in future IC designs without incurring prohibitive overheads.\n\nThis invention provides a solution that dramatically reduces fuseROM footprint, lowers power consumption, and enhances the scalability of memory repair, directly addressing these critical challenges in modern semiconductor manufacturing.","question":"What problem does Optimizing Fuserom Usage for Memory Repair solve?"},{"answer":"The patent for Optimizing Fuserom Usage for Memory Repair (US-9852810) does not list specific inventors in the provided data. However, patents like this are typically the result of extensive research and development efforts by teams of engineers and scientists within semiconductor companies or research institutions. The innovation reflects a deep understanding of integrated circuit design, memory architectures, and defect management strategies.\n\nSuch inventions are crucial for advancing the capabilities and reliability of the electronic devices we use daily. While the individual inventors' names are not provided in this specific context, the collective expertise in the field of microelectronics drives these breakthroughs, pushing the boundaries of what's possible in chip technology. The patent was filed on June 8, 2015, and published on December 26, 2017.","question":"Who invented Optimizing Fuserom Usage for Memory Repair?"},{"answer":"Optimizing Fuserom Usage for Memory Repair offers several key benefits that are highly advantageous for the semiconductor industry and, by extension, for end-users:\n\n1.  **Reduced Chip Area and Cost:** By minimizing the required fuseROM footprint, manufacturers can produce smaller dies, leading to more chips per wafer and significantly lower production costs. This directly impacts the affordability of electronic devices.\n2.  **Enhanced Reliability and Yields:** The efficient and targeted repair mechanism ensures that memory defects are effectively addressed, resulting in more reliable integrated circuits and higher manufacturing yields.\n3.  **Lower Power Consumption:** Fewer fuse read operations during repair processes lead to reduced power consumption, which is critical for battery-powered devices and energy-efficient data centers.\n4.  **Improved Scalability:** The dynamic allocation of repair resources allows for the integration of larger and denser memory arrays in future IC designs without the traditional penalties, enabling continuous technological advancement.\n\nThese benefits collectively contribute to more advanced, cost-effective, and dependable electronic products across a wide range of applications.","question":"What are the key benefits of Optimizing Fuserom Usage for Memory Repair?"},{"answer":"Optimizing Fuserom Usage for Memory Repair significantly differentiates itself from prior art by moving away from static, blanket fuseROM allocation to a dynamic, two-stage, and highly targeted repair data management system.\n\nPrior art often involved dedicating a fixed amount of fuseROM for every potential memory block repair, even if the block was perfectly healthy. This resulted in considerable waste of chip area and power. While other methods like ECC (Error Correction Codes) or BISR (Built-In Self-Repair) exist, they often still rely on an underlying fuseROM structure that can suffer from similar overheads or have limitations in the types of errors they can correct.\n\nThis invention's unique contribution is its 'memory bypass chain' for rapid defect identification and a 're-configurable memory data chain' for selective repair data loading. This intelligent, conditional approach ensures that fuseROM resources are only engaged when and where truly needed, offering superior efficiency, scalability, and cost-effectiveness compared to previous solutions. It shifts the paradigm from 'prepare for everything' to 'address only what's broken, efficiently.'","question":"How is Optimizing Fuserom Usage for Memory Repair different from prior art?"},{"answer":"Optimizing Fuserom Usage for Memory Repair has the potential to impact virtually all industries that rely on advanced integrated circuits (ICs) and embedded memory. Its benefits in terms of cost reduction, enhanced reliability, and improved scalability make it valuable across a broad spectrum of applications.\n\nKey industries include:\n\n*   **Consumer Electronics:** Smartphones, tablets, laptops, smart home devices, where compact size, low power, and high reliability are paramount.\n*   **Automotive:** Advanced driver-assistance systems (ADAS), infotainment, and engine control units, which demand extremely high levels of reliability and safety.\n*   **Data Centers & High-Performance Computing (HPC):** Servers, network equipment, and AI accelerators, where memory density, speed, and uptime are critical.\n*   **Internet of Things (IoT):** Edge devices and sensors, requiring ultra-low power consumption and small form factors.\n*   **Industrial & Medical:** Control systems, diagnostic equipment, and wearable medical devices, where robust and dependable operation is essential.\n\nThis technology will enable these industries to develop more powerful, efficient, and reliable products, driving innovation and market growth.","question":"What industries will Optimizing Fuserom Usage for Memory Repair impact?"},{"answer":"The patent for Optimizing Fuserom Usage for Memory Repair was filed on June 8, 2015. This date marks the official submission of the invention's detailed description and claims to the patent office, initiating the examination process. The publication date, which is when the patent application (or granted patent) becomes publicly available, was December 26, 2017.\n\nThis timeline indicates the period of review and examination by the patent office before the invention was officially published. The publication of the patent means that the details of this innovative memory repair system are now publicly accessible, allowing other researchers, engineers, and companies to understand its scope and implications. It signifies a recognized advancement in the field of integrated circuit design and memory reliability.","question":"When was Optimizing Fuserom Usage for Memory Repair filed/granted?"},{"answer":"The commercial applications of Optimizing Fuserom Usage for Memory Repair are extensive, primarily revolving around enabling the production of more competitive, reliable, and cost-effective integrated circuits (ICs). Its core value lies in optimizing the manufacturing process and enhancing product quality.\n\nKey commercial applications include:\n\n*   **Cost Reduction in Chip Manufacturing:** Semiconductor companies can achieve significant cost savings by reducing the die size and increasing the number of functional chips per wafer.\n*   **Product Differentiation:** Manufacturers can market their products as having superior reliability, lower power consumption, and smaller form factors, gaining a competitive edge.\n*   **Enabling High-Density Memory Products:** The scalability of this technology allows for the design and production of ICs with larger and more complex embedded memory arrays, opening doors for new product categories in AI, advanced computing, and data storage.\n*   **IP Licensing Opportunities:** The patent holder could license the intellectual property to other semiconductor design houses and foundries, generating revenue through royalties.\n\nUltimately, this innovation supports the broader market demand for more efficient, powerful, and dependable electronic devices across all sectors.","question":"What are the commercial applications of Optimizing Fuserom Usage for Memory Repair?"},{"answer":"The principles established by Optimizing Fuserom Usage for Memory Repair lay a strong foundation for exciting future developments in integrated circuit (IC) reliability and memory management. We can anticipate several advancements building upon this intelligent fuseROM optimization strategy.\n\nFuture developments might include:\n\n*   **Adaptive Repair Algorithms:** Integrating machine learning to dynamically adjust repair strategies based on real-time operational data and historical defect patterns, making repair even more intelligent and predictive.\n*   **Multi-Layered Fault Tolerance:** Combining this efficient repair with advanced error correction codes (ECC) for an even more robust and resilient memory subsystem, capable of handling a wider range of errors.\n*   **System-Level Optimization:** Extending the concept of dynamic, conditional resource allocation beyond memory repair to other configurable elements within an SoC, optimizing for power, performance, and reliability across the entire chip.\n*   **In-Field Reconfigurability:** Enabling more sophisticated in-field repair or re-configuration capabilities, potentially extending the lifespan of devices and reducing maintenance costs.\n\nThese developments will push ICs towards truly self-healing and adaptive systems, crucial for the increasing complexity and mission-critical applications of future technology, ensuring continued advancements in performance and reliability.","keywords":["future memory repair","IC development roadmap","self-healing chips","adaptive semiconductor technology","fuseROM advancements","integrated circuit reliability trends"],"question":"What are the future developments expected for Optimizing Fuserom Usage for Memory Repair?"}],"topics":["memory repair","fuseROM optimization","integrated circuit reliability","IC memory systems","semiconductor repair","relentless","demand","higher"],"tech_cluster":null},"seo":{"title":"Optimizing Fuserom Usage for Memory Repair - Patent US-9852810","description":"Discover Optimizing Fuserom Usage for Memory Repair, a patent for efficient IC memory repair. Reduces fuseROM, boosts reliability, and cuts costs. Full analysis.","keywords":["memory repair","fuseROM optimization","integrated circuit reliability","IC memory systems","semiconductor repair","defective memory bypass","chip design","patent US-9852810","memory wrapper","fuse register","bypass register","fuseROM controller","memory bypass chain"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852810","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852810","citation_suggestion":"Patentable. \"Optimizing fuseROM usage for memory repair\" (US-9852810). https://patentable.app/patents/US-9852810","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852810","json":"https://patentable.app/api/llm-context/US-9852810","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:14:13.560Z"}