{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852908","patent":{"patent_number":"US-9852908","title":"Methods for integrated circuit design and fabrication","assignee":null,"inventors":[],"filing_date":"2016-06-06T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein."},"analysis":{"summary":"The patent titled \"Methods for Integrated Circuit Design and Fabrication\" (US-9852908) introduces a sophisticated and highly effective technique for patterning target material layers on semiconductor substrates. At its core, this innovation addresses the critical challenge of manufacturing integrated circuits with increasingly smaller and more precise features, which is fundamental to advancing computing power and electronic device capabilities.\n\nThis patent filing describes a multi-step process that ingeniously combines spacer technology with photolithographic patterning. The method begins by forming a 'spacer feature' over the target material layer using a first sub-layout. This spacer acts as a high-precision, temporary template. Subsequently, a photolithographic process, guided by a second sub-layout, is used to form a 'first feature.' A key aspect of this invention is that a portion of this newly formed first feature is designed to extend specifically over the pre-existing spacer feature.\n\nThe innovation then proceeds with two crucial removal steps: first, the precise removal of the portion of the first feature that extends over the spacer feature, effectively trimming or refining the pattern. Second, the subsequent removal of the spacer feature itself. This sequential, self-aligned approach allows for the creation of patterns with superior resolution, critical dimension uniformity, and reduced line edge roughness compared to traditional single-step lithography or even some multi-patterning techniques.\n\nThe business value and market opportunity for Methods for Integrated Circuit Design and Fabrication are substantial. This technology enables semiconductor manufacturers to produce next-generation chips with higher yields and potentially lower costs by extending the capabilities of existing equipment. It supports the ongoing miniaturization demanded by artificial intelligence, high-performance computing, IoT, and advanced mobile devices. By providing a reliable method for nanoscale patterning, this patent helps accelerate innovation across the entire electronics industry, offering a competitive advantage to companies that adopt this advanced fabrication methodology.","layman_explanation":"### What Problem Does This Solve?\nImagine the world of modern electronics – from your smartphone to massive data centers. All of these rely on integrated circuits, or 'chips,' which are essentially tiny cities of interconnected pathways. For these devices to get faster, smaller, and more powerful, those pathways need to shrink to incredibly microscopic sizes. The biggest challenge has been how to 'draw' these super-tiny, perfect lines and shapes onto silicon wafers without errors. Current methods, often relying on light (photolithography), hit physical limits; it's like trying to write a novel with a crayon. The lines become blurry, uneven, or simply too large, leading to defective chips and higher manufacturing costs. This patent, \"Methods for Integrated Circuit Design and Fabrication,\" directly addresses this fundamental bottleneck, enabling the continued miniaturization that drives technological progress.\n\n### How Does It Work?\nThis innovation isn't about inventing a new, exotic drawing tool, but rather a smarter, more precise way to use existing ones. Think of it like a master sculptor using a series of clever steps to create a highly intricate carving. Instead of trying to carve the whole thing at once, which would be prone to error, the Methods for Integrated Circuit Design and Fabrication patent uses a multi-stage approach:\n\n1.  **Setting a 'Guide Rail':** First, they lay down a super-accurate, temporary 'guide rail' or 'spacer feature' on the chip's surface. This rail is formed with exceptional precision, acting as a perfect template.\n2.  **Rough Sketching with Refinement:** Then, they use a standard light-based 'drawing' process (photolithography) to create a broader pattern. Crucially, this pattern is designed to intentionally overlap with the precise 'guide rail' in certain areas. It's like making a slightly oversized sketch that extends beyond a perfect straightedge.\n3.  **Precision Trimming:** The ingenious next step is to 'trim' away only the parts of the rough sketch that extend beyond the guide rail. This is done with a highly controlled process, essentially using the perfect edge of the guide rail to define the final, incredibly precise shape.\n4.  **Removing the Guide:** Finally, the temporary 'guide rail' is removed, leaving behind only the perfectly sculpted, ultra-fine pattern on the chip. This sequential process allows for a level of accuracy and smallness that would be impossible with a single, direct 'drawing' step.\n\n### Why Does This Matter?\nThis method matters immensely because it directly impacts the fundamental economics and performance of the electronics industry. By enabling the creation of smaller, more accurate features, this patent drives several key business advantages:\n\n*   **Market Leadership:** Companies adopting this technology can produce more advanced, powerful, and energy-efficient chips, gaining a competitive edge in markets like AI processors, high-performance computing, and next-generation mobile devices.\n*   **Cost Efficiency:** It extends the life and capabilities of existing manufacturing equipment, reducing the need for immediate, multi-billion-dollar investments in entirely new, more expensive lithography tools. This translates to lower capital expenditure and potentially higher profit margins.\n*   **Higher Yields:** More precise patterning means fewer defective chips on each wafer, leading to higher manufacturing yields. This directly improves profitability and reduces waste.\n*   **Innovation Acceleration:** This approach unlocks new possibilities for chip design, allowing engineers to create even more complex and functional circuits, thereby accelerating innovation across the entire tech ecosystem.\n\n### What's Next?\nThe \"Methods for Integrated Circuit Design and Fabrication\" patent provides a robust foundation for continued miniaturization in the semiconductor industry. We can expect to see this approach, or variations of it, becoming standard for manufacturing chips at 7nm, 5nm, and even smaller nodes. Its future applications will likely include next-generation memory, advanced logic processors, and specialized AI accelerators, all demanding the highest levels of patterning precision. For investors, this represents a technology that enables sustained growth and profitability in the semiconductor sector, offering a strategic pathway to overcome physical scaling limits and continue delivering the innovation that powers our digital world.","technical_analysis":"The patent \"Methods for Integrated Circuit Design and Fabrication\" (US-9852908) presents a novel and technically significant approach to patterning semiconductor substrates, crucial for the continued scaling of integrated circuits. This invention addresses the inherent limitations of conventional photolithography as feature sizes shrink to the nanoscale, where diffraction and resolution become major bottlenecks.\n\n**Technical Architecture and Algorithm Specifics:**\nAt its core, this patent describes a hybrid patterning methodology that synergistically integrates self-aligned spacer technology with traditional photolithography. The process flow is meticulously designed to achieve superior pattern fidelity and critical dimension control. The fundamental steps are:\n\n1.  **Initial Layer Preparation:** A target material layer (e.g., polysilicon, metal, dielectric) is deposited over a semiconductor substrate. This layer will ultimately be patterned to form the desired circuit features.\n2.  **Spacer Feature Formation (First Sub-layout):**\n    *   A sacrificial material (e.g., amorphous silicon, silicon nitride) is deposited conformally over an initial patterned feature (defined by a 'first sub-layout' using conventional lithography and etch). This initial feature acts as a mandrel.\n    *   An anisotropic etch-back process is then performed, removing the sacrificial material from horizontal surfaces and leaving behind highly uniform 'spacer features' on the sidewalls of the mandrel. These spacers are characterized by excellent critical dimension uniformity (CDU) and line edge roughness (LER), as their width is controlled by deposition thickness rather than lithographic resolution.\n3.  **Photolithographic Patterning (Second Sub-layout):**\n    *   A photoresist layer is applied over the substrate, now containing the spacer features.\n    *   A second photolithographic patterning process is performed using a 'second sub-layout.' This sub-layout is designed to create a 'first feature' in the photoresist (and subsequently in the underlying layers after etch) such that a specific portion of this first feature *extends over* one of the previously formed spacer features. This overlap is a deliberate and critical design choice, not an accidental misalignment.\n4.  **Selective Removal of Overlapping Portion:**\n    *   An etch process is executed to selectively remove the portion of the photolithographically defined first feature that overlaps the spacer feature. This step effectively 'trims' or 'shapes' the larger, lithographically defined feature using the precise edge of the spacer as a guide. The etch must be highly selective to the photoresist and the target material layer, while being non-selective or having very low selectivity to the spacer material.\n5.  **Spacer Feature Removal:**\n    *   Finally, the spacer feature itself is removed. This typically involves a highly selective wet or dry etch that removes the spacer material without damaging the newly patterned target material layer. This leaves behind the final, precisely defined circuit feature.\n\n**Implementation Details and Integration Patterns:**\nThis method is highly adaptable and can be integrated into various process flows for manufacturing advanced FinFET gates, interconnects, and memory cell structures. The selection of materials for the target layer, spacer, and sacrificial layers is crucial, requiring careful consideration of etch selectivity and deposition characteristics. For example, if the target layer is polysilicon, the spacer might be silicon nitride, and the sacrificial mandrel could be silicon oxide. The 'first sub-layout' and 'second sub-layout' refer to the design patterns used for the lithography masks, which must be carefully co-optimized to ensure the correct overlap and subsequent trimming.\n\n**Performance Characteristics and Code-Level Implications:**\n*   **Resolution Enhancement:** By using the spacer as a high-resolution template for trimming, the effective resolution of the patterned feature can be significantly higher than what the photolithographic step alone could achieve. This enables patterning at sub-lithographic pitches.\n*   **Improved CDU and LER:** The inherent precision of spacer formation directly contributes to better CDU and LER for the final features, which is critical for device performance and yield.\n*   **Defectivity Reduction:** The self-aligned nature of the process can reduce certain types of pattern-related defects that arise from misalignment in other multi-patterning techniques.\n*   **Design-for-Manufacturability (DFM):** This approach necessitates advanced DFM tools and methodologies. Layout decomposition, mask synthesis, and optical proximity correction (OPC) algorithms must be sophisticated enough to generate the optimal 'first' and 'second' sub-layouts, ensuring proper overlap and etch windows.\n*   **Process Control:** Tight control over deposition thicknesses, etch rates, and selectivities is paramount to ensure the desired pattern transfer and avoid unintended material removal.\n\nIn essence, this patent provides a powerful methodology for extending the capabilities of existing lithography infrastructure while paving the way for even finer feature definition. It's a testament to the continuous innovation in process engineering required to sustain the advancement of integrated circuit technology.","business_analysis":"The patent \"Methods for Integrated Circuit Design and Fabrication\" (US-9852908) represents a significant business opportunity and strategic advantage within the intensely competitive semiconductor industry. This innovation directly addresses critical manufacturing challenges, offering tangible benefits that can reshape market dynamics and investment returns.\n\n**Market Opportunity Size:** The global semiconductor manufacturing market is a multi-trillion-dollar industry, with integrated circuit fabrication forming its core. As demand for AI, IoT, 5G, and high-performance computing explodes, the need for smaller, faster, and more energy-efficient chips is paramount. This patent enables the production of such advanced chips, placing it at the heart of a market worth hundreds of billions annually, with specific relevance to advanced logic and memory manufacturing (e.g., 14nm, 10nm, 7nm, and beyond process nodes).\n\n**Competitive Advantages:**\n1.  **Cost-Effective Scaling:** One of the most compelling advantages is the ability to achieve finer feature resolution without requiring immediate, massive investments in next-generation extreme ultraviolet (EUV) lithography tools. This patent allows manufacturers to extend the lifespan and capabilities of existing deep ultraviolet (DUV) lithography equipment, significantly reducing capital expenditure while still enabling node migration.\n2.  **Higher Yields & Performance:** By improving pattern fidelity, critical dimension uniformity (CDU), and reducing line edge roughness (LER), this technology leads to higher manufacturing yields. Fewer defective chips mean more sellable products, directly impacting profitability. Furthermore, more precise patterning translates to better device performance, attracting premium customers and market share.\n3.  **Accelerated Time-to-Market:** The robustness and precision of this method can streamline process development for new technology nodes, potentially shortening the design-to-production cycle for advanced chips. This agility is a key competitive differentiator in a fast-moving market.\n4.  **IP Protection & Licensing Potential:** Holding a patent on such a fundamental fabrication method provides a strong defensive and offensive IP position. It offers potential for licensing revenue from other foundries or integrated device manufacturers (IDMs) seeking to implement similar advanced patterning techniques.\n\n**Revenue Potential and Business Models:** Companies owning or licensing this technology can realize revenue through:\n*   **Direct Manufacturing:** Foundries (e.g., TSMC, Samsung Foundry, Intel Foundry Services) can use this to produce higher-value, higher-margin advanced chips for their clients.\n*   **IP Licensing:** Licensing the patent to other semiconductor manufacturers or equipment suppliers.\n*   **Tool & Material Sales:** Equipment manufacturers (e.g., ASML, Lam Research, Applied Materials) could develop tools and materials optimized for this specific multi-patterning process, creating new revenue streams.\n\n**Strategic Positioning:** This invention strategically positions a company as a leader in advanced semiconductor manufacturing. It is a foundational technology that underpins the development of next-generation processors for AI accelerators, data centers, mobile devices, and autonomous driving. Companies adopting this approach can solidify their market leadership, attract top talent, and secure long-term contracts with major tech innovators.\n\n**ROI Projections:** While specific ROI depends on implementation scale and market adoption, the benefits are clear. A 5-10% increase in yield for advanced nodes, coupled with deferred capital expenditures on new lithography tools (potentially billions of dollars), represents a massive return on investment. Reduced defect rates and faster product cycles further enhance profitability. This patent offers a pathway to sustained profitability and growth in an industry where incremental gains in efficiency and precision translate into significant financial advantages. The ability to produce smaller, more powerful, and cheaper chips is a perpetual driver of demand, and this patent directly facilitates that.","faqs":[{"answer":"Methods for Integrated Circuit Design and Fabrication (US-9852908) is a groundbreaking patent that describes an advanced technique for patterning target material layers over semiconductor substrates. Essentially, it's a sophisticated method for 'drawing' the incredibly tiny lines and shapes that make up computer chips with extreme precision.\n\nThis innovation addresses the challenges faced by traditional photolithography as chip features shrink to nanoscale dimensions. It combines the advantages of self-aligned spacer technology with conventional light-based patterning to achieve superior resolution and control.\n\nBy enabling finer and more accurate patterns, the Methods for Integrated Circuit Design and Fabrication patent is crucial for manufacturing next-generation integrated circuits that are faster, smaller, and more energy-efficient. It's a key enabler for advancements in various high-tech fields.\n\nKeywords: integrated circuit design, semiconductor fabrication, nanoscale patterning, photolithography, chip manufacturing.","question":"What is Methods for Integrated Circuit Design and Fabrication?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent employs a multi-step, hybrid patterning process. It starts by forming a highly precise 'spacer feature' on the semiconductor substrate using a first design layout. This spacer acts as a temporary, high-resolution template.\n\nNext, a photolithographic patterning process is performed using a second design layout to create a 'first feature.' A critical aspect of this step is that a portion of this newly formed first feature is intentionally designed to extend over the previously created spacer feature. This overlap is a deliberate design choice.\n\nThe innovation then proceeds with two crucial removal steps: first, the precise removal of the portion of the 'first feature' that extends over the spacer, effectively trimming the pattern using the spacer's precise edge as a guide. Second, the subsequent removal of the spacer feature itself. This sequential, self-aligned approach results in highly accurate and resolved circuit patterns.\n\nKeywords: spacer feature, photolithography, sub-layout, pattern trimming, self-aligned patterning, semiconductor process.","question":"How does Methods for Integrated Circuit Design and Fabrication work?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent solves the escalating challenge of patterning nanoscale features on semiconductor wafers with sufficient precision and cost-effectiveness. As integrated circuits continue to shrink, traditional photolithography methods encounter fundamental physical limits, leading to issues like poor resolution, critical dimension non-uniformity, and high defect rates.\n\nThese problems directly impact manufacturing yields, increase production costs, and limit the performance and power efficiency of advanced chips. The invention provides a robust solution to overcome these limitations, enabling the continued miniaturization and performance enhancement required by Moore's Law.\n\nBy offering a more precise and reliable patterning method, this patent helps the industry push beyond current manufacturing bottlenecks, fostering innovation in all areas reliant on advanced electronics.\n\nKeywords: nanoscale patterning, photolithography limits, semiconductor challenges, critical dimension control, manufacturing defects, chip miniaturization.","question":"What problem does Methods for Integrated Circuit Design and Fabrication solve?"},{"answer":"The specific inventors of the Methods for Integrated Circuit Design and Fabrication patent (US-9852908) are not listed in the provided data, nor is the assignee. However, such complex innovations typically originate from research and development teams within leading semiconductor companies, academic institutions, or specialized R&D firms.\n\nThese teams comprise experts in materials science, electrical engineering, physics, and process engineering, all working collaboratively to push the boundaries of microchip fabrication. The development of such a patent requires extensive knowledge of lithography, etching, deposition, and semiconductor device physics.\n\nRegardless of the specific individuals, the invention represents a significant contribution to the collective knowledge and capabilities of the semiconductor industry.\n\nKeywords: patent inventors, semiconductor R&D, integrated circuit innovation, patent assignee, technology development.","question":"Who invented Methods for Integrated Circuit Design and Fabrication?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent offers several crucial benefits for the semiconductor industry and, by extension, for all electronic devices. Firstly, it enables significantly enhanced pattern resolution, allowing for the creation of smaller and denser circuit features than previously possible with conventional methods. This is fundamental for continued miniaturization.\n\nSecondly, it leads to improved critical dimension uniformity (CDU) and reduced line edge roughness (LER). These improvements are vital for achieving higher manufacturing yields, as more chips on a wafer will meet performance specifications, reducing waste and cost. Better pattern fidelity also translates directly to enhanced device performance and reliability.\n\nFinally, this technology provides a cost-effective pathway to advanced process nodes. By extending the capabilities of existing lithography equipment, it can reduce the immediate need for massive capital investments in next-generation tools, thereby optimizing capital expenditure for manufacturers. These benefits collectively drive higher profitability and accelerated innovation across the electronics sector.\n\nKeywords: enhanced resolution, critical dimension uniformity, higher yields, cost-effective manufacturing, device performance, semiconductor benefits.","question":"What are the key benefits of Methods for Integrated Circuit Design and Fabrication?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent distinguishes itself from prior art by offering a unique hybrid multi-patterning approach. Unlike single-exposure lithography, which struggles with sub-wavelength features, this invention combines spacer technology with photolithography to achieve finer patterns.\n\nCompared to Litho-Etch-Litho-Etch (LELE) techniques, this patent reduces sensitivity to overlay errors because the critical dimension is defined by the self-aligned spacer rather than the precise alignment of multiple lithographic steps. While Self-Aligned Double/Quadruple Patterning (SADP/SAQP) offers excellent CD control, it is typically limited to simple line-and-space patterns. The Methods for Integrated Circuit Design and Fabrication approach provides greater flexibility for complex 2D patterns by using photolithography for broader definition which is then refined by the spacer.\n\nFurthermore, it offers a more immediate and cost-effective solution for advanced nodes compared to the multi-billion-dollar investment required for Extreme Ultraviolet (EUV) lithography. This patent provides a strategic bridge technology, enhancing existing capabilities while addressing core patterning challenges.\n\nKeywords: prior art comparison, multi-patterning, SADP, LELE, EUV, lithography differences, competitive advantage, process innovation.","question":"How is Methods for Integrated Circuit Design and Fabrication different from prior art?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent will have a profound impact across virtually all industries that rely on advanced electronic devices. Its primary impact will be in the **semiconductor manufacturing** industry itself, enabling foundries and integrated device manufacturers to produce next-generation chips more efficiently and precisely.\n\nConsequently, it will significantly influence the **consumer electronics** sector, leading to smaller, faster, and more energy-efficient smartphones, laptops, wearables, and smart home devices. The **artificial intelligence (AI)** and **high-performance computing (HPC)** industries will also benefit immensely, as this technology enables the creation of more powerful processors for AI training, data centers, and supercomputers.\n\nOther impacted sectors include **automotive (for autonomous driving and in-car infotainment systems), telecommunications (for 5G infrastructure and devices), aerospace and defense, medical devices, and the Internet of Things (IoT)**. Essentially, any industry driven by the need for advanced microchips will see direct benefits from the capabilities offered by Methods for Integrated Circuit Design and Fabrication.\n\nKeywords: semiconductor industry, consumer electronics, AI, high-performance computing, IoT, automotive, 5G, technology impact.","question":"What industries will Methods for Integrated Circuit Design and Fabrication impact?"},{"answer":"The patent titled \"Methods for Integrated Circuit Design and Fabrication\" was filed on **June 6, 2016**. This date marks when the inventors submitted their application to the patent office, initiating the examination process.\n\nIt was subsequently published on **December 26, 2017**. The publication date typically signifies when the patent application becomes publicly accessible, allowing others to review the details of the invention.\n\nThese dates are important for understanding the timeline of the innovation and its position within the broader landscape of intellectual property in semiconductor technology. They indicate the period during which the technology was conceived, developed, and brought to the attention of the public and industry.\n\nKeywords: patent filing date, publication date, patent timeline, US-9852908, intellectual property, semiconductor history.","question":"When was Methods for Integrated Circuit Design and Fabrication filed/granted?"},{"answer":"The commercial applications of the Methods for Integrated Circuit Design and Fabrication patent are extensive and critical for the advancement of modern technology. Primarily, it enables the **mass production of advanced integrated circuits** for leading-edge technology nodes (e.g., 7nm, 5nm, and beyond). This includes logic chips (CPUs, GPUs), memory chips (DRAM, NAND flash), and specialized processors.\n\nSpecifically, this technology is vital for fabricating high-performance components used in **AI accelerators, data center servers, high-end smartphones, and autonomous driving systems**. Its ability to achieve high precision and yield at nanoscale makes it ideal for complex, high-value chips where performance and power efficiency are paramount.\n\nFurthermore, the patent supports the development of smaller, more efficient chips for **IoT devices and wearable technology**, allowing for greater functionality in compact form factors. It also contributes to the cost-effective scaling of semiconductor manufacturing, providing a strategic advantage for companies in a capital-intensive industry. The commercial viability lies in its ability to deliver superior products at competitive costs.\n\nKeywords: commercial applications, integrated circuit production, AI chips, data center components, smartphone processors, IoT devices, semiconductor market, manufacturing scalability.","question":"What are the commercial applications of Methods for Integrated Circuit Design and Fabrication?"},{"answer":"The Methods for Integrated Circuit Design and Fabrication patent lays a robust foundation for future developments in semiconductor patterning. We can anticipate continued optimization of this hybrid approach, potentially through integration with other emerging technologies.\n\nOne key area of future development could involve combining this method with **Directed Self-Assembly (DSA)** techniques, where materials spontaneously arrange into precise patterns, offering even finer resolution and potentially reducing lithography steps. Further advancements in **material science** will also play a role, with the development of novel spacer materials and target layers that offer even higher etch selectivities and improved performance characteristics.\n\nAs chips move towards **3D integration and heterogeneous integration**, the principles of precise patterning and self-alignment described in this patent will become even more critical for defining vertical interconnects and stacking multiple chiplets. Expect to see enhanced **computational lithography and Design-for-Manufacturability (DFM) tools** that can more intelligently optimize the sub-layouts and process parameters for even more complex designs. The core concepts of Methods for Integrated Circuit Design and Fabrication will continue to be refined to meet the ever-increasing demands of next-generation electronics.\n\nKeywords: future semiconductor technology, 3D integration, Directed Self-Assembly, material science, computational lithography, DFM tools, chip scaling, process innovation.","question":"What are the future developments expected for Methods for Integrated Circuit Design and Fabrication?"}],"topics":["integrated circuit design","semiconductor fabrication","nanoscale patterning","photolithography","spacer feature","relentless","scaling","integrated"],"tech_cluster":null},"seo":{"title":"Methods for Integrated Circuit Design and Fabrication - Patent US-9852908","description":"Discover the 'Methods for Integrated Circuit Design and Fabrication' patent (US-9852908) for advanced nanoscale patterning. Achieve superior precision, higher yields, and cost-effective chip manufacturing.","keywords":["integrated circuit design","semiconductor fabrication","nanoscale patterning","photolithography","spacer feature","chip manufacturing","advanced lithography","US-9852908 patent","semiconductor innovation","critical dimension control","microchip technology","fabrication methods"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852908","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852908","citation_suggestion":"Patentable. \"Methods for integrated circuit design and fabrication\" (US-9852908). https://patentable.app/patents/US-9852908","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852908","json":"https://patentable.app/api/llm-context/US-9852908","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:36:09.638Z"}