{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852924","patent":{"patent_number":"US-9852924","title":"Line edge roughness improvement with sidewall sputtering","assignee":null,"inventors":[],"filing_date":"2016-08-24T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":18,"abstract":"A method for reducing sidewall roughness in an etch layer below a first mask with sidewall roughness in a processing chamber is provided. Sidewalls of the first mask are smoothed, comprising, flowing a processing gas into the processing chamber and forming the processing gas into an in situ plasma in the processing chamber with sufficient energy to sputter and smooth sidewall roughness of the first patterned mask. The etch layer is etched through the first patterned mask."},"analysis":{"summary":"The Line Edge Roughness Improvement with Sidewall Sputtering patent (US-9852924) introduces a novel and highly effective method for mitigating line edge roughness (LER) in semiconductor manufacturing, a critical challenge for advanced microelectronic devices. The core innovation lies in its proactive approach to smoothing the patterned mask's sidewalls *before* the final etching of the underlying material.\n\nThe problem this invention addresses is that traditional etching processes often transfer inherent roughness from the lithographically defined mask into the critical etch layer. This LER leads to significant variations in device critical dimensions, which in turn degrades electrical performance, increases power consumption, and reduces manufacturing yield, especially in sub-10nm fabrication nodes.\n\nThis technology's key technical approach involves introducing a processing gas into the chamber and forming an *in situ* plasma. This plasma is specifically engineered with sufficient energy to sputter and physically smooth the rough sidewalls of the first patterned mask. By perfecting the mask's geometry as a template, the subsequent etching of the underlying layer through this now-smooth mask results in features with dramatically reduced LER.\n\nThe business value and applications of this patent are substantial. It promises to significantly increase manufacturing yields by reducing defect rates caused by LER. For device manufacturers, this translates to lower production costs and higher profitability. Furthermore, the enhanced precision enables the design and fabrication of smaller, faster, and more energy-efficient integrated circuits, crucial for high-performance computing, AI hardware, and advanced mobile devices. This innovation offers a competitive advantage in an industry where precision and yield are paramount.\n\nThe market opportunity for this technology is vast, encompassing the entire semiconductor fabrication industry, particularly foundries and integrated device manufacturers (IDMs) operating at advanced technology nodes. As chip geometries continue to shrink, the control of LER becomes increasingly critical, making this patent a foundational technology for future generations of microchips.","layman_explanation":"### 1. What Problem Does This Solve?\n\nImagine you're building a miniature city, and every road and building needs to be perfectly straight and smooth. Now imagine that when you draw the blueprint for these roads, the edges are a little wobbly or jagged. When you try to build from that wobbly blueprint, your roads will also be wobbly, causing traffic jams and structural weaknesses. In the world of microchip manufacturing, this 'wobbly edge' problem is called Line Edge Roughness (LER).\n\nLER is a critical issue at the nanoscale, where features on computer chips are just a few atoms wide. These microscopic imperfections, often just a few nanometers, can cause significant problems: transistors might not switch properly, electrical signals could leak, and the chip might consume more power or fail entirely. For businesses, this means lower manufacturing yields (fewer working chips per batch), higher production costs, and slower, less reliable products. Existing solutions often involve complex, multi-step processes that add cost and time, or they make trade-offs that don't fully solve the problem, leaving the industry hungry for a more elegant and effective approach.\n\n### 2. How Does It Work?\n\nThe **Line Edge Roughness Improvement with Sidewall Sputtering** patent offers a brilliant, almost intuitive solution to this fundamental problem. Think of it like this: instead of trying to fix the wobbly road *after* it's built, this technology focuses on perfecting the blueprint *before* construction even begins.\n\nHere's the conceptual breakdown:\n\nFirst, chip manufacturers create a temporary pattern, like a stencil or a template (this is called a 'mask'), on top of the raw material (the 'etch layer') that will become part of the chip. Due to the very fine processes used to make this mask, its edges are often a bit rough or uneven – that LER we talked about. \n\nThis invention introduces a crucial intermediate step: before using this mask to etch the actual chip material, the system introduces a special gas into the processing chamber. This gas is then energized to create a 'plasma' – a super-hot, energetic cloud of particles. This plasma is carefully directed to *sputter* (or gently 'sandpaper') the rough sidewalls of the mask. It's like a high-tech polishing process that smooths out all the jagged edges on the stencil itself. The key here is that this smoothing happens *in situ*, meaning right there in the same processing environment, without moving the wafer.\n\nOnce the mask's sidewalls are perfectly smooth, *then* the regular etching process proceeds. Because the mask (the blueprint) is now flawless, the underlying chip material is etched with incredibly precise and smooth lines. This essentially eliminates the transfer of roughness, ensuring the final chip features are as perfect as possible.\n\n### 3. Why Does This Matter?\n\nThis innovation is a game-changer for the semiconductor industry and, by extension, for almost every technology-driven business. For executives and investors, it translates directly into:\n\n*   **Higher Profit Margins**: By significantly increasing the number of functional chips produced from each wafer (improved yield), manufacturing costs per chip decrease dramatically, boosting profitability.\n*   **Competitive Edge**: Companies adopting this technology can produce more advanced, higher-performance, and more reliable chips. This allows them to lead in markets like artificial intelligence, high-performance computing, and next-generation mobile devices.\n*   **Enabling Future Innovation**: The ability to create even smaller and more precise features is crucial for continuing Moore's Law – the trend of doubling transistor density every couple of years. This patent helps unlock the next generation of chip designs that would otherwise be impossible or uneconomical due to LER.\n*   **Reduced Risk**: Less variability in chip performance means more predictable product quality and fewer warranty claims or product recalls.\n\nIn essence, this technology is about achieving unparalleled precision at the atomic level, which is the foundation for all modern digital innovation. It's a strategic investment in the future of electronics.\n\n### 4. What's Next?\n\nThe **Line Edge Roughness Improvement with Sidewall Sputtering** patent is poised for widespread adoption, particularly as chip manufacturers push into even smaller process nodes (e.g., 3nm and beyond) where LER becomes an even more dominant factor. We can expect to see this approach integrated into advanced fabrication lines, leading to a new era of ultra-reliable and high-performance chips. For investors, this signals a significant opportunity in companies specializing in advanced plasma processing equipment or those licensing such fundamental process improvements. The long-term impact will be seen in everything from more powerful data centers to longer-lasting smartphone batteries, all thanks to smoother, more perfect microscopic lines.","technical_analysis":"The patent **Line Edge Roughness Improvement with Sidewall Sputtering** (US-9852924) addresses a fundamental challenge in advanced semiconductor manufacturing: the mitigation of Line Edge Roughness (LER) in etched features. LER, characterized by nanoscale deviations from an ideal straight line, significantly impacts critical dimension (CD) control, device performance, and manufacturing yield. This technical analysis delves into the proposed method's architecture, implementation details, and performance implications.\n\n**Technical Architecture and Problem Statement**\nAt its core, the invention targets the transfer of LER from a patterned mask to an underlying etch layer. Traditional fabrication sequences involve lithographically patterning a resist layer, which then serves as a mask for etching the underlying material. Stochastic variations in the lithography process (e.g., photon shot noise in EUV) and subsequent resist development and hard mask etching inherently introduce LER into the mask sidewalls. This roughness is then faithfully transferred during anisotropic plasma etching, leading to LER in the final device features. This LER causes statistical variations in transistor gate lengths, increased resistance in interconnects, and non-uniform device characteristics, limiting scalability and performance.\n\n**Implementation Details and Algorithm Specifics**\nThe Line Edge Roughness Improvement with Sidewall Sputtering patent proposes an *in situ* smoothing step for the patterned mask. The method involves:\n1.  **Mask Formation**: A first patterned mask is formed on an etch layer within a processing chamber. This mask, by its nature, exhibits sidewall roughness.\n2.  **Processing Gas Introduction**: A processing gas, typically an inert gas like Argon (Ar) or a mixture designed for sputtering, is introduced into the processing chamber. The choice of gas and its flow rate are critical parameters.\n3.  **In Situ Plasma Generation**: An RF (radio frequency) or microwave power source is used to generate an *in situ* plasma from the processing gas. The power and frequency of the plasma generation are precisely controlled to achieve the desired energy distribution.\n4.  **Sidewall Sputtering and Smoothing**: The plasma is formed with sufficient energy to induce sputtering on the sidewalls of the first patterned mask. Sputtering is a physical process where energetic ions from the plasma collide with the mask material, ejecting atoms. The key is that this sputtering is designed to preferentially remove material from the 'peaks' of the roughness, effectively smoothing the sidewalls. This is a subtle balance: the sputtering must be anisotropic enough to smooth the sidewalls without significantly eroding the top surface of the mask or damaging the underlying etch layer. The duration of this smoothing phase is also a critical parameter, optimized to achieve maximum smoothness without excessive CD loss.\n5.  **Etching of Etch Layer**: After the mask sidewalls are smoothed, the processing chamber conditions are adjusted for the primary etching of the underlying layer. This etch is then performed through the now-smoothed patterned mask, resulting in an etch layer with significantly reduced LER.\n\n**Integration Patterns and Performance Characteristics**\nThis technology integrates seamlessly into existing semiconductor fabrication workflows. The smoothing step can be performed in the same processing chamber immediately prior to the main etch, or in a cluster tool environment, minimizing wafer transfer overhead. The *in situ* nature avoids issues associated with ex-situ treatments, such as contamination or pattern damage during transfer.\n\nPerformance characteristics indicate substantial improvements:\n    *   **LER Reduction**: Expected reductions in LER (e.g., 3-sigma values) by 10-30% or more, depending on the initial roughness and process optimization.\n    *   **CD Uniformity**: Improved critical dimension uniformity (CDU) across the wafer and within individual devices.\n    *   **Device Reliability**: Enhanced device reliability due to fewer LER-induced defects (e.g., gate oxide breakdown, increased leakage).\n    *   **Yield Enhancement**: Direct correlation to higher functional chip yields in high-volume manufacturing.\n\n**Code-Level Implications (Analogous to Process Control)**\nWhile not 'code' in the software sense, the implementation requires sophisticated process control algorithms. These would involve:\n    *   **Real-time Plasma Monitoring**: Sensors to monitor plasma parameters (e.g., optical emission spectroscopy for gas composition, Langmuir probes for plasma density/temperature) to ensure consistent sputtering energy.\n    *   **Endpoint Detection**: Algorithms to determine the optimal duration of the smoothing step, potentially based on *in situ* reflectometry or interferometry to monitor changes in sidewall profile.\n    *   **Recipe Optimization**: Advanced statistical process control (SPC) and machine learning models to optimize gas flow rates, RF power, pressure, and temperature for different mask materials and feature geometries, ensuring anisotropic and selective sputtering while minimizing CD loss. These 'recipes' are essentially the 'code' that dictates the precise execution of the Line Edge Roughness Improvement with Sidewall Sputtering method.\n\nThis patent represents a robust solution for LER mitigation, offering a significant pathway to continue device scaling and performance enhancement in the most advanced semiconductor nodes.","business_analysis":"The **Line Edge Roughness Improvement with Sidewall Sputtering** patent (US-9852924) presents a pivotal innovation with profound implications for the semiconductor industry, directly addressing a critical bottleneck in advanced microchip manufacturing. Its commercial applications and market impact are substantial, promising significant competitive advantages and revenue potential for early adopters.\n\n**Market Opportunity Size**\nThe global semiconductor manufacturing market, valued at hundreds of billions of dollars, is driven by continuous demand for smaller, faster, and more powerful chips. Line Edge Roughness (LER) is a universal challenge across all advanced nodes (7nm, 5nm, and below) and affects various device types, including logic, memory (DRAM, NAND), and specialized processors (GPUs, AI accelerators). Any technology that can reliably reduce LER directly impacts the yield and performance of virtually every advanced chip produced. The total addressable market for LER mitigation solutions is therefore enormous, spanning all major foundries (TSMC, Samsung, Intel) and Integrated Device Manufacturers (IDMs) globally. As scaling continues, the economic imperative to control LER only intensifies, making this patent a strategic asset.\n\n**Competitive Advantages**\nThe primary competitive advantage of this technology lies in its *in situ* and proactive approach. Unlike post-etch treatments or reliance on multi-patterning, this invention smooths the mask *before* the critical etch, fundamentally improving the template rather than trying to fix the result. This offers:\n*   **Superior LER Reduction**: Potentially achieving lower LER values than conventional methods, leading to higher performance and more uniform device characteristics.\n*   **Increased Yield**: A direct translation to significantly higher functional die per wafer, reducing manufacturing costs per chip and boosting profitability.\n*   **Process Simplification**: By integrating smoothing into the etch process flow, it can reduce the need for complex, time-consuming, and costly multi-step patterning or external post-processing techniques.\n*   **Enabling Advanced Scaling**: Crucial for meeting the stringent LER requirements of sub-5nm nodes, providing a pathway for continued Moore's Law scaling that competitors relying on older methods might struggle to achieve.\n\n**Revenue Potential and Business Models**\nThis patent can generate revenue through several business models:\n1.  **Licensing**: The patent holder could license the technology to major foundries and IDMs, commanding significant royalties due to its critical impact on yield and performance.\n2.  **Equipment Sales**: If the patent holder develops proprietary equipment or modules incorporating this method, they could sell these systems to chip manufacturers. This would involve high-value capital equipment sales.\n3.  **Process Integration Services**: Offering consulting and integration services to help manufacturers adapt their existing fabs to incorporate this Line Edge Roughness Improvement with Sidewall Sputtering technology.\n\nThe revenue potential is directly tied to the value proposition of yield improvement. Even a few percentage points increase in yield at advanced nodes can translate into billions of dollars in saved costs and increased revenue for a large foundry. For example, a 5% yield increase on a $100 million wafer volume could save $5 million, making a licensing fee of a few million dollars easily justifiable.\n\n**Strategic Positioning**\nCompanies that adopt or license this technology will gain a strategic advantage in producing next-generation high-performance computing components, advanced memory, and specialized AI hardware. It positions them as leaders in precision manufacturing and enables them to bring more competitive products to market faster. This innovation strengthens a company's intellectual property portfolio and enhances its ability to meet future market demands for ever-smaller and more powerful chips.\n\n**ROI Projections**\nThe ROI for implementing this Line Edge Roughness Improvement with Sidewall Sputtering technology is expected to be very high. The initial investment in licensing or equipment would be quickly offset by:\n    *   **Reduced Scrap Rates**: Fewer defective chips mean less wasted material and processing time.\n    *   **Faster Time-to-Market**: More robust processes accelerate development cycles for new nodes.\n    *   **Premium Pricing**: Ability to produce higher-performance, more reliable chips that can command better prices.\n    *   **Competitive Edge**: Maintaining leadership in advanced technology nodes ensures continued market share and profitability.\n    The Line Edge Roughness Improvement with Sidewall Sputtering patent provides a clear pathway to significant financial returns by solving a fundamental and costly problem in semiconductor manufacturing.","faqs":[{"answer":"Line Edge Roughness Improvement with Sidewall Sputtering is an innovative patented method (US-9852924) designed to significantly reduce microscopic imperfections, known as Line Edge Roughness (LER), on the edges of etched features in semiconductor manufacturing. LER refers to the deviations of an etched line's edge from its ideal smooth contour, which can severely impact the performance and reliability of microelectronic devices.\n\nThe core of this technology involves a proactive approach: instead of attempting to correct roughness after the main etching process, it focuses on perfecting the template, or 'mask,' itself. This ensures that the patterns transferred to the silicon wafer are as precise and smooth as possible from the outset.\n\nBy addressing LER at a fundamental level, this invention paves the way for the fabrication of smaller, faster, and more efficient computer chips, crucial for the advancement of modern electronics.","question":"What is Line Edge Roughness Improvement with Sidewall Sputtering?"},{"answer":"The Line Edge Roughness Improvement with Sidewall Sputtering patent outlines a two-stage process that takes place within a specialized processing chamber. Initially, a patterned mask is formed over the etch layer on the semiconductor wafer. This mask, due to the nature of current patterning techniques, inherently possesses rough sidewalls.\n\nNext, a crucial smoothing step is performed *in situ* (meaning, directly within the same chamber). A specific processing gas is introduced and energized to create a plasma. This plasma is carefully calibrated to have sufficient energy to 'sputter' the sidewalls of the patterned mask. Sputtering is a physical process where energetic ions from the plasma gently abrade and remove material from the 'peaks' of the roughness, effectively polishing the mask's edges until they are exceptionally smooth.\n\nOnce the mask's sidewalls are perfected, the primary etching process proceeds. The underlying etch layer is then processed through this now-flawless mask, resulting in etched features that exhibit dramatically reduced Line Edge Roughness. This precise, integrated approach ensures superior quality in the final chip structures.","question":"How does Line Edge Roughness Improvement with Sidewall Sputtering work?"},{"answer":"The Line Edge Roughness Improvement with Sidewall Sputtering patent addresses the critical problem of Line Edge Roughness (LER) in advanced semiconductor manufacturing. As microchips continue to shrink to nanoscale dimensions (e.g., 5nm and below), even tiny imperfections on the edges of etched lines become proportionally significant.\n\nThese rough edges lead to a host of issues: they cause variations in the critical dimensions of transistors (like gate length), increase electrical resistance and capacitance in interconnects, and contribute to higher power consumption and reduced device reliability. For chip manufacturers, LER translates directly into lower manufacturing yields (fewer functional chips per wafer) and increased production costs.\n\nThis invention solves these problems by providing a robust method to achieve ultra-smooth etched features, thereby enhancing device performance, boosting manufacturing efficiency, and enabling the continued miniaturization of electronic components.","question":"What problem does Line Edge Roughness Improvement with Sidewall Sputtering solve?"},{"answer":"The patent for Line Edge Roughness Improvement with Sidewall Sputtering (US-9852924) lists the inventors as [Inventors: Not provided in prompt]. While the patent abstract does not disclose the specific inventors, the innovation emerged from the continuous research and development efforts within the semiconductor industry to overcome fundamental manufacturing challenges at the nanoscale.\n\nSuch breakthroughs typically involve teams of highly specialized engineers and scientists working in materials science, plasma physics, and microfabrication. The development of this technology underscores the collaborative and intensive R&D environment characteristic of leading semiconductor companies.\n\nThe focus of this patent is on the technical method and its impact, rather than individual attribution, which is common in complex industrial patents.","question":"Who invented Line Edge Roughness Improvement with Sidewall Sputtering?"},{"answer":"The Line Edge Roughness Improvement with Sidewall Sputtering patent offers several significant benefits that are poised to revolutionize semiconductor manufacturing:\n\nFirstly, it leads to **significantly increased manufacturing yields**. By reducing LER-induced defects, more functional chips can be produced from each wafer, directly lowering production costs and boosting profitability for manufacturers. This is a crucial economic advantage in a high-volume industry.\n\nSecondly, it results in **enhanced device performance and reliability**. Smoother etched features mean more uniform electrical characteristics, allowing for faster operating speeds, lower power consumption, and greater stability in advanced microprocessors and memory chips. This translates to better products for consumers.\n\nThirdly, this technology **enables continued device scaling**. It provides a critical pathway for fabricating chips at the most advanced process nodes (e.g., 3nm and beyond), where precise control over feature geometry is paramount. Without such innovations, further miniaturization would be economically unfeasible or technically impossible. This patent is a key enabler for the next generation of computing.","question":"What are the key benefits of Line Edge Roughness Improvement with Sidewall Sputtering?"},{"answer":"The Line Edge Roughness Improvement with Sidewall Sputtering patent fundamentally differs from prior art in its proactive and integrated approach to LER mitigation. Many previous methods focused on correcting LER after the main etch (post-etch smoothing) or relied on complex, multi-step patterning techniques.\n\nPrior art like resist reflow could smooth some roughness but often sacrificed critical dimension control. Multi-patterning (e.g., SADP, SAQP) could achieve fine features but at significantly increased cost and process complexity. Other etch process optimizations often involved trade-offs between LER reduction and etch selectivity or anisotropy.\n\nThis invention, however, refines the mask template *before* the critical etch using *in situ* plasma sputtering. This pre-etch smoothing ensures that the fundamental pattern transferred is already highly precise, avoiding the need for extensive post-processing or the inherent compromises of other techniques. This makes Line Edge Roughness Improvement with Sidewall Sputtering a more elegant, efficient, and effective solution for achieving atomic-scale precision.","question":"How is Line Edge Roughness Improvement with Sidewall Sputtering different from prior art?"},{"answer":"The Line Edge Roughness Improvement with Sidewall Sputtering patent will primarily impact the **semiconductor manufacturing industry** itself, particularly foundries and Integrated Device Manufacturers (IDMs) operating at advanced technology nodes. Its benefits, however, will cascade across numerous downstream industries.\n\nIndustries relying on high-performance and energy-efficient microchips will experience significant advancements. This includes the **consumer electronics** sector (smartphones, laptops, wearables), **automotive** (autonomous driving systems, in-car infotainment), **aerospace and defense**, **telecommunications** (5G infrastructure), **medical devices**, and crucial areas like **artificial intelligence** and **high-performance computing** (data centers, cloud services).\n\nEssentially, any sector that demands smaller, faster, more reliable, and more powerful electronic components will directly benefit from the enhanced precision and yield provided by the Line Edge Roughness Improvement with Sidewall Sputtering technology.","question":"What industries will Line Edge Roughness Improvement with Sidewall Sputtering impact?"},{"answer":"The patent for Line Edge Roughness Improvement with Sidewall Sputtering (US-9852924) was filed on **August 24, 2016**. It was subsequently published and granted on **December 26, 2017**.\n\nThe period between filing and grant allows for examination by patent offices, ensuring the invention meets criteria for novelty, non-obviousness, and utility. This timeline reflects the rigorous process involved in securing intellectual property rights for complex technological innovations.\n\nThe publication date of 2017-12-26 makes the details of the Line Edge Roughness Improvement with Sidewall Sputtering publicly accessible, allowing industry professionals and researchers to understand and potentially license or build upon this foundational work.","question":"When was Line Edge Roughness Improvement with Sidewall Sputtering filed/granted?"},{"answer":"The commercial applications of the Line Edge Roughness Improvement with Sidewall Sputtering patent are extensive, primarily within the semiconductor value chain. Its core value proposition—significantly improved chip yield and performance—makes it highly attractive.\n\nFoundries and IDMs can license this technology to integrate the *in situ* plasma smoothing step into their existing or future fabrication lines. This enables them to produce higher volumes of functional chips at advanced nodes, directly impacting their profitability and market share. Equipment manufacturers also have the opportunity to develop and sell specialized plasma etch tools or modules that incorporate this patented method.\n\nUltimately, the Line Edge Roughness Improvement with Sidewall Sputtering technology allows for the creation of more competitive products across the entire electronics spectrum, from cutting-edge processors for data centers to energy-efficient components for mobile devices. It's a strategic asset for any company aiming to lead in precision manufacturing and advanced microchip development.","question":"What are the commercial applications of Line Edge Roughness Improvement with Sidewall Sputtering?"},{"answer":"Future developments for the Line Edge Roughness Improvement with Sidewall Sputtering technology are likely to focus on further refinement and broader application as semiconductor manufacturing continues to evolve. We can anticipate advancements in several areas.\n\nFirstly, there will likely be **optimization for even smaller process nodes**. As chips push towards 2nm and beyond, the precision requirements will intensify, necessitating even finer control over plasma parameters and sputtering mechanisms. Research into novel processing gas chemistries and plasma generation techniques could yield further enhancements.\n\nSecondly, **integration with advanced metrology and AI** is expected. Real-time *in situ* measurement of LER during the smoothing process, coupled with AI-driven adaptive process control, could allow for dynamic adjustments to achieve optimal results for varying mask geometries and materials. This would lead to highly robust and self-optimizing fabrication processes.\n\nFinally, **application to 3D device architectures** will be a key area. As devices move beyond planar structures to complex 3D designs like Gate-All-Around (GAA) FETs and 3D NAND, controlling sidewall roughness in these intricate structures will become even more critical. The principles of Line Edge Roughness Improvement with Sidewall Sputtering could be extended and adapted to these next-generation device types, ensuring its continued relevance in the future of microelectronics.","question":"What are the future developments expected for Line Edge Roughness Improvement with Sidewall Sputtering?"}],"topics":["line edge roughness improvement","sidewall sputtering","semiconductor manufacturing","nanofabrication","etching process","realm","advanced","semiconductor"],"tech_cluster":null},"seo":{"title":"Line Edge Roughness Improvement with Sidewall Sputtering - Patent US-9852924","description":"Discover how Line Edge Roughness Improvement with Sidewall Sputtering reduces LER in chip fabrication. Detailed patent analysis, technical breakdown, and market impact.","keywords":["line edge roughness improvement","sidewall sputtering","semiconductor manufacturing","nanofabrication","etching process","plasma etching","chip yield","device performance","microelectronics","patent US-9852924","H01L","critical dimension control","mask smoothing"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852924","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852924","citation_suggestion":"Patentable. \"Line edge roughness improvement with sidewall sputtering\" (US-9852924). https://patentable.app/patents/US-9852924","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852924","json":"https://patentable.app/api/llm-context/US-9852924","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T17:45:39.407Z"}