{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852947","patent":{"patent_number":"US-9852947","title":"Forming sidewall spacers using isotropic etch","assignee":null,"inventors":[],"filing_date":"2016-09-21T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method includes etching a dielectric layer to form an opening, with a component of a transistor being exposed through the opening. A spacer layer is formed, and includes a horizontal portion at a bottom of the opening, and a vertical portion in the opening. The vertical portion is on a sidewall of the dielectric layer. An isotropic etch is performed on the spacer layer to remove the horizontal portion, and the vertical portion remains after the isotropic etch. The remaining vertical portion forms a contact plug spacer. A conductive material is filled into the opening to form a contact plug."},"analysis":{"summary":"The patent \"Forming Sidewall Spacers Using Isotropic Etch\" introduces a groundbreaking method for manufacturing critical components within semiconductor devices, specifically contact plug spacers. This innovation addresses the pervasive challenge of achieving precise electrical isolation in ever-shrinking transistor geometries, a key bottleneck in advanced microchip fabrication.\n\nThe core problem this invention solves is the difficulty in reliably creating uniform and defect-free sidewall spacers using conventional anisotropic etching techniques. These traditional methods can be complex, prone to causing damage, or leaving unwanted material residues, directly impacting device performance and manufacturing yield.\n\nThis patent outlines a technical approach that begins by etching an opening in a dielectric layer, exposing a transistor component. Subsequently, a spacer layer is formed, which includes both a horizontal portion at the bottom of the opening and a vertical portion along the sidewalls. The ingenuity lies in the next step: an isotropic etch is performed to selectively remove only the horizontal portion of this spacer layer. This leaves the vertical portion intact, which then precisely forms the contact plug spacer. Finally, a conductive material is filled into the opening to complete the contact plug.\n\nThe business value and applications of this technology are substantial. By simplifying and making more precise a critical fabrication step, this method can significantly improve manufacturing yields, reduce production costs, and enhance the reliability and performance of semiconductor devices. It enables more aggressive scaling of transistors, which is essential for developing next-generation processors, memory, and specialized AI hardware.\n\nThe market opportunity for this kind of process improvement is immense, impacting the entire semiconductor industry. Any manufacturer striving for higher density, faster, and more energy-efficient chips stands to benefit, potentially leading to widespread adoption in advanced process nodes. This innovation provides a robust foundation for continued technological advancement in electronics.","layman_explanation":"### What Problem Does This Solve?\nImagine you're building a miniature city, and within that city, you need to lay down super-tiny electrical wires (which we call 'contact plugs' in a microchip). These wires need to be perfectly insulated from other nearby structures, like tiny buildings (transistor components), to prevent them from short-circuiting. The 'insulation' comes in the form of incredibly thin walls, known as 'sidewall spacers.'\n\nThe challenge, especially as our chips get smaller and smaller, is consistently making these walls perfectly. Traditional methods are often like trying to carve a delicate structure with a blunt tool: they can be imprecise, leave behind unwanted debris, or even damage the surrounding delicate components. This leads to faulty chips, wasted production, and higher costs for manufacturers. Essentially, the problem is achieving perfect, reliable insulation at an atomic scale without damaging the complex neighborhood around it.\n\n### How Does It Work?\nThe patent, \"Forming Sidewall Spacers Using Isotropic Etch,\" offers a remarkably elegant solution. Think of it like this: first, a tiny trench is dug in the ground (a dielectric layer). At the bottom of this trench, a small part of your 'building' (transistor component) is exposed. Next, a special 'coating material' (the spacer layer) is applied, which covers both the floor of the trench and its vertical walls, much like a thin blanket.\n\nNow, here's the clever part: instead of trying to carve away the unwanted material, a 'special cleaning fluid' (an isotropic etch) is used. This fluid is designed to *uniformly dissolve* only the flat coating material on the floor of the trench, while leaving the coating on the vertical walls completely untouched and perfectly shaped. Once the floor is clean, you're left with pristine, perfectly formed vertical insulating walls. Then, you simply fill the trench with your electrical 'wire material' (conductive material) to complete the contact plug. It's a method that leverages smart chemistry to achieve precision, rather than brute-force carving.\n\n### Why Does This Matter?\nThis innovation matters immensely for several reasons. Firstly, it directly translates to **higher manufacturing yields**. By making the spacer formation process more reliable and less prone to defects, chip manufacturers can produce more working chips from each wafer, significantly reducing waste and increasing profitability. Secondly, it leads to **better performing and more reliable devices**. When these tiny insulating walls are perfect, the electrical connections are cleaner, leading to faster, more energy-efficient, and longer-lasting microchips. This impacts everything from the smartphones in our pockets to the powerful servers driving artificial intelligence.\n\nFrom a market perspective, this patent provides a crucial **competitive advantage**. Companies adopting this technology can build next-generation processors and memory chips with superior characteristics, allowing them to lead in the race for technological advancement. It reduces production complexity and cost, making advanced chip manufacturing more accessible and efficient.\n\n### What's Next?\nThe principles behind \"Forming Sidewall Spacers Using Isotropic Etch\" are likely to see broad adoption in the semiconductor industry, particularly as chip designs continue to shrink. We can expect to see this technology integrated into the fabrication processes for future generations of processors, memory, and specialized chips for AI and IoT. For investors, this represents an opportunity to back companies that are solving fundamental manufacturing challenges, enabling the continued exponential growth of computing power and pushing the boundaries of what's possible in electronics.","technical_analysis":"The patent \"Forming Sidewall Spacers Using Isotropic Etch\" (US-9852947) details a sophisticated method for fabricating dielectric sidewall spacers, crucial components for electrical isolation in advanced semiconductor devices. This technical analysis will delve into the architecture, implementation details, and performance implications of this innovative etching technique.\n\n**Technical Architecture and Problem Statement:**\nModern transistors, particularly those in advanced nodes (e.g., FinFET, GAA), require extremely precise contact plugs to establish electrical connections. These plugs must be electrically isolated from adjacent gate electrodes or other active regions by dielectric sidewall spacers. Traditional methods often involve depositing a conformal dielectric film and then performing an anisotropic reactive ion etch (RIE) to remove horizontal portions, leaving vertical spacers. However, anisotropic etches face significant challenges at nanoscale: aspect ratio dependent etching (ARDE), micro-trenching, re-deposition, and potential damage to underlying layers. These issues compromise spacer uniformity, electrical integrity, and overall device yield.\n\n**Implementation Details and Algorithm Specifics:**\n1.  **Opening Formation:** The process begins with etching a dielectric layer to form an opening. This opening exposes a component of a transistor (e.g., a source/drain region, gate contact area). The etching for this initial opening can be a conventional anisotropic dry etch, carefully controlled to achieve the desired dimensions and profile.\n2.  **Spacer Layer Deposition:** A spacer layer is then conformally deposited. This means the layer forms uniformly over the existing topography, resulting in a horizontal portion at the bottom of the opening and a vertical portion along the sidewalls of the dielectric layer. Common materials for this spacer layer include silicon nitride (SiN), silicon dioxide (SiO2), or other low-k dielectrics, deposited using techniques like atomic layer deposition (ALD) or chemical vapor deposition (CVD) to ensure conformality.\n3.  **Isotropic Etch Performance:** The core innovation lies here. An isotropic etch is performed on the deposited spacer layer. Unlike anisotropic etches, an isotropic etch removes material uniformly in all directions (laterally and vertically). The critical aspect is the *selectivity* and *duration* of this etch. The etch chemistry and parameters are chosen such that:\n    *   It effectively removes the horizontal portion of the spacer layer at the bottom of the opening.\n    *   It has high selectivity to the underlying transistor component and the primary dielectric layer, preventing damage.\n    *   It removes the horizontal portion completely without significantly eroding the critical vertical portion, which is relatively thicker or protected by its geometry.\n    *   Examples of isotropic etches could include wet chemical etches (e.g., dilute hydrofluoric acid for SiO2) or plasma-based isotropic dry etches (e.g., using F-based chemistries in a low-power, high-pressure plasma for SiN or SiO2). The choice depends on the specific materials and desired selectivity.\n4.  **Remaining Vertical Portion:** After the isotropic etch, the horizontal portion is completely removed, leaving behind only the vertical portion of the spacer layer. This precisely defined vertical feature then functions as the contact plug spacer, providing the necessary electrical isolation.\n5.  **Conductive Material Fill:** Finally, a conductive material (e.g., tungsten, copper) is filled into the opening, completing the formation of the contact plug.\n\n**Integration Patterns and Performance Characteristics:**\nThis method seamlessly integrates into existing semiconductor fabrication flows. It replaces or refines the traditional anisotropic spacer etch step, offering a more robust alternative. The key advantage is the potential for superior uniformity of spacer dimensions across a wafer, reducing variability and improving statistical process control. The isotropic nature of the etch, when applied selectively to a horizontal layer, can mitigate ARDE effects often seen in anisotropic trench etching. This leads to cleaner interfaces, reduced leakage currents, lower contact resistance, and ultimately, enhanced device performance and reliability.\n\n**Code-Level Implications (Analogous to process recipes):**\nIn a fabrication plant, this translates to refined process recipes. Engineers would develop and validate specific etch chemistries, gas flows, power levels, and etch durations (analogous to 'code parameters') to achieve the desired isotropic removal with high selectivity. The 'algorithm' involves a sequence of deposition and etching steps, where the isotropic etch is a precisely controlled 'function' called at a specific point in the fabrication 'program'. Monitoring tools (e.g., optical emission spectroscopy, in-situ metrology) would provide real-time feedback to ensure the 'code' (recipe) executes as intended.\n\nIn summary, the Forming Sidewall Spacers Using Isotropic Etch patent offers a technically sound and elegant solution to a critical problem in advanced IC manufacturing. By judiciously employing an isotropic etch for selective material removal, this invention promises to enhance precision, yield, and performance, paving the way for further miniaturization and innovation in semiconductor technology.","business_analysis":"The patent \"Forming Sidewall Spacers Using Isotropic Etch\" (US-9852947) represents a significant process innovation with substantial implications for the semiconductor industry. This business impact analysis will explore the market opportunity, competitive advantages, revenue potential, business models, strategic positioning, and ROI projections for this groundbreaking technology.\n\n**Market Opportunity Size:**\nThe semiconductor manufacturing market is projected to reach over $600 billion by 2025, driven by demand for advanced computing, AI, IoT, and 5G. Within this, the fabrication equipment and materials segment, directly impacted by this patent, is a multi-billion dollar market. Specifically, etching and deposition processes are core to all chip manufacturing. As feature sizes continue to shrink (sub-10nm nodes), the precision and yield challenges addressed by this patent become exponentially more critical. The market for solutions that enhance yield and performance at these advanced nodes is immense and growing, as even a fractional improvement can translate to billions in revenue for chipmakers.\n\n**Competitive Advantages:**\nThis innovation provides several key competitive advantages:\n1.  **Improved Yield:** By offering a more controlled and precise method for forming critical sidewall spacers, the patent can significantly reduce defects, leading to higher manufacturing yields. This is a direct cost saving for chipmakers.\n2.  **Enhanced Performance & Reliability:** Cleaner, more uniform spacers result in better electrical isolation, lower leakage currents, and improved device reliability and performance, giving products built with this technology a competitive edge.\n3.  **Simplified Process Flow:** Replacing complex, multi-parameter anisotropic etches with a more straightforward isotropic removal step can simplify process integration, reduce cycle times, and potentially lower equipment maintenance costs.\n4.  **Scalability:** The robustness of this method makes it highly adaptable to future generations of semiconductor devices, ensuring long-term relevance and investment protection.\n\n**Revenue Potential & Business Models:**\nCompanies that develop or license this technology could realize revenue through several avenues:\n*   **Equipment Sales:** Manufacturers of etching equipment could integrate this process into their next-generation tools, offering enhanced capabilities.\n*   **Materials Sales:** Developers of specialized etch chemistries or precursor materials for the spacer layer could see increased demand.\n*   **IP Licensing:** Semiconductor foundries (e.g., TSMC, Samsung Foundry, Intel Foundry Services) and Integrated Device Manufacturers (IDMs like Intel, Micron) could license the patent to improve their in-house fabrication processes.\n*   **Consulting/Services:** Expertise in implementing this advanced etching technique could be offered as a high-value consulting service.\n\n**Strategic Positioning:**\nAdopting the principles of \"Forming Sidewall Spacers Using Isotropic Etch\" strategically positions a company as a leader in advanced semiconductor manufacturing. It signals a commitment to overcoming fundamental physical limitations in chip scaling, enabling the production of cutting-edge processors and memory. For foundries, it translates to offering superior process capabilities, attracting high-value customers. For IDMs, it means producing more competitive and higher-performing chips in-house.\n\n**ROI Projections:**\nWhile specific ROI will vary, the potential returns are substantial due to the high-volume, high-value nature of semiconductor manufacturing:\n*   **Yield Improvement:** A 1% increase in yield for a leading-edge foundry can translate to hundreds of millions, if not billions, of dollars in annual revenue.\n*   **Cost Reduction:** Simplified processes, reduced rework, and lower defect rates directly decrease operational expenditures.\n*   **Time-to-Market:** More efficient and reliable fabrication accelerates product development cycles, providing a critical competitive advantage in a rapidly evolving market.\n\nIn conclusion, \"Forming Sidewall Spacers Using Isotropic Etch\" is not merely a technical refinement but a strategic business enabler. Its ability to enhance precision, yield, and reliability in semiconductor manufacturing positions it as a critical innovation for companies seeking to dominate the advanced node market and drive the future of digital technology.","faqs":[{"answer":"Forming Sidewall Spacers Using Isotropic Etch refers to a patented method (US-9852947) for creating critical insulating structures, known as sidewall spacers, within semiconductor devices. These spacers are essential for electrically isolating contact plugs from other components of a transistor, preventing short circuits and ensuring proper device function.\n\nThe innovation lies in its unique approach to material removal. Instead of using complex, often problematic, anisotropic etching techniques to define the vertical shape of the spacers, this patent leverages an isotropic etch to selectively remove unwanted horizontal material from a pre-deposited layer.\n\nThis method simplifies a key fabrication step, making it more precise and reliable. It's a foundational technology that contributes to the ability to build smaller, more powerful, and more energy-efficient microchips for all modern electronics. The Forming Sidewall Spacers Using Isotropic Etch patent outlines a specific sequence of deposition and etching to achieve this crucial insulating structure.","question":"What is Forming Sidewall Spacers Using Isotropic Etch?"},{"answer":"The Forming Sidewall Spacers Using Isotropic Etch patent describes a multi-step process. First, an opening is created in a dielectric (insulating) layer, exposing a component of a transistor. This opening defines where a contact plug will eventually be formed.\n\nNext, a spacer layer, typically a dielectric material, is deposited conformally. This means the layer forms uniformly over the existing topography, creating a horizontal portion at the bottom of the opening and vertical portions along the sidewalls of the dielectric layer.\n\nThen, the core innovation comes into play: an isotropic etch is performed. This etch is precisely controlled to selectively remove *only* the horizontal portion of the spacer layer at the bottom of the opening. The vertical portions, which are the desired sidewall spacers, remain intact. Finally, a conductive material is filled into the opening, now perfectly isolated by the remaining vertical spacers, to form the contact plug. This selective removal is key to the efficiency and precision of Forming Sidewall Spacers Using Isotropic Etch.","question":"How does Forming Sidewall Spacers Using Isotropic Etch work?"},{"answer":"Forming Sidewall Spacers Using Isotropic Etch solves the significant challenge of reliably and precisely manufacturing insulating sidewall spacers in advanced semiconductor devices. As transistors continue to shrink to nanoscale dimensions, achieving perfect electrical isolation for contact plugs becomes incredibly difficult.\n\nTraditional methods often rely on anisotropic etching, which can suffer from issues like non-uniform material removal, micro-trenching, re-deposition of etched material, and potential damage to delicate underlying transistor components. These problems lead to manufacturing defects, reduced chip yield, compromised device performance (e.g., increased leakage currents), and higher production costs.\n\nThis patent provides a robust solution that mitigates these issues by offering a more controlled and less damaging way to define the spacers. By simplifying the etch process, Forming Sidewall Spacers Using Isotropic Etch helps overcome a critical bottleneck in the fabrication of next-generation microchips.","question":"What problem does Forming Sidewall Spacers Using Isotropic Etch solve?"},{"answer":"The patent US-9852947 for Forming Sidewall Spacers Using Isotropic Etch was filed on September 21, 2016, and published on December 26, 2017. The inventors and assignee are not provided in the abstract, description, or claims sections of the patent data. Typically, this information is found on the front page of the granted patent document.\n\nHowever, the innovation itself stems from the ongoing collaborative research and development efforts within the semiconductor industry, where teams of engineers, material scientists, and process experts continually push the boundaries of microchip fabrication. The principles outlined in Forming Sidewall Spacers Using Isotropic Etch represent a collective advancement in etching technologies crucial for modern electronics. Further details on the specific inventors would require consulting the full patent document from official patent databases.","question":"Who invented Forming Sidewall Spacers Using Isotropic Etch?"},{"answer":"The Forming Sidewall Spacers Using Isotropic Etch patent offers several significant benefits for semiconductor manufacturing. Firstly, it leads to **higher manufacturing yields** by reducing defects associated with spacer formation. A more controlled etching process means fewer faulty chips and more usable product per wafer.\n\nSecondly, it results in **enhanced device performance and reliability**. Precisely formed and damage-free sidewall spacers ensure superior electrical isolation, leading to lower leakage currents, reduced contact resistance, faster switching speeds, and overall more robust and efficient transistors. This directly translates to better-performing electronic devices.\n\nThirdly, the method can **simplify the fabrication process**. By replacing complex, multi-parameter anisotropic etches with a more straightforward isotropic removal step, it can reduce process complexity, shorten cycle times, and potentially lower equipment and operational costs. These advantages make Forming Sidewall Spacers Using Isotropic Etch a highly valuable innovation.","question":"What are the key benefits of Forming Sidewall Spacers Using Isotropic Etch?"},{"answer":"Forming Sidewall Spacers Using Isotropic Etch significantly differentiates itself from prior art primarily in its etching methodology. Traditional prior art techniques largely rely on **anisotropic etching** to define sidewall spacers. Anisotropic etches remove material preferentially in one direction, aiming to create vertical features by etching away horizontal layers.\n\nHowever, as chip features shrink, anisotropic etches face challenges like aspect ratio dependent etching (ARDE), micro-trenching, and potential damage to underlying layers. The Forming Sidewall Spacers Using Isotropic Etch patent, by contrast, uses an **isotropic etch**. Instead of using this etch to *define* the vertical shape, it uses it to *selectively remove* the unwanted horizontal portion of a *pre-deposited conformal spacer layer*.\n\nThis distinction is crucial. By focusing the isotropic etch on removing a blanket horizontal film, the process can be more uniform, less damaging, and more forgiving than trying to precisely sculpt vertical features with an anisotropic etch at extreme scales. This shift in approach provides a more robust and reliable method for spacer formation, offering a competitive advantage over conventional techniques.","question":"How is Forming Sidewall Spacers Using Isotropic Etch different from prior art?"},{"answer":"Forming Sidewall Spacers Using Isotropic Etch will primarily impact the **semiconductor manufacturing industry**, which is the foundation for virtually all modern electronics. Any company involved in the fabrication of integrated circuits, from leading foundries to Integrated Device Manufacturers (IDMs), stands to benefit from this innovation.\n\nBeyond direct manufacturing, its influence extends to industries that rely on advanced microchips. This includes the **consumer electronics sector** (smartphones, laptops, wearables), **automotive industry** (for advanced driver-assistance systems and infotainment), **telecommunications** (5G infrastructure), **artificial intelligence and machine learning** (AI accelerators and data center processors), and **high-performance computing**.\n\nBy enabling the production of more efficient, powerful, and reliable chips, Forming Sidewall Spacers Using Isotropic Etch indirectly supports the growth and innovation across a vast array of technology-driven markets, underpinning the digital transformation of the global economy.","question":"What industries will Forming Sidewall Spacers Using Isotropic Etch impact?"},{"answer":"The patent for Forming Sidewall Spacers Using Isotropic Etch (US-9852947) has a **filing date of September 21, 2016**. This is the date when the patent application was submitted to the patent office.\n\nThe patent was subsequently **published on December 26, 2017**. The publication date typically signifies when the patent document becomes publicly accessible, irrespective of whether it has been officially granted yet.\n\nThese dates are important for understanding the timeline of the innovation and its position within the broader landscape of semiconductor technology development. The period between filing and publication allows for examination by patent authorities, while the publication itself ensures transparency and establishes prior art for other inventors. The issuance of a patent often follows the publication after further examination and potential amendments. The Forming Sidewall Spacers Using Isotropic Etch patent's timeline reflects a typical progression for such complex technical innovations.","question":"When was Forming Sidewall Spacers Using Isotropic Etch filed/granted?"},{"answer":"The commercial applications of Forming Sidewall Spacers Using Isotropic Etch are extensive and critical to the modern technology landscape. Primarily, it enables the **mass production of advanced microchips** with higher yields and improved performance. This means more powerful and reliable processors for everything from personal computers and servers to specialized AI chips and embedded systems.\n\nSpecifically, it facilitates the manufacturing of **next-generation consumer electronics**, allowing for thinner, lighter, and more energy-efficient devices like smartphones, tablets, and smart wearables. In the **automotive sector**, it supports the creation of sophisticated chips for autonomous driving, in-car entertainment, and safety systems.\n\nFurthermore, this technology is vital for the development of **high-performance computing (HPC)** and **data center infrastructure**, where demand for faster and more reliable processors is constant. It also plays a key role in **5G technology** and the **Internet of Things (IoT)**, by enabling the production of smaller, more power-efficient components. The core process improvement offered by Forming Sidewall Spacers Using Isotropic Etch underpins nearly all cutting-edge electronic product development.","question":"What are the commercial applications of Forming Sidewall Spacers Using Isotropic Etch?"},{"answer":"Future developments related to Forming Sidewall Spacers Using Isotropic Etch are expected to focus on further optimizing its integration into increasingly complex semiconductor architectures and pushing its capabilities to even smaller nodes. We can anticipate advancements in:\n\n**1. Enhanced Material Selectivity:** Ongoing research will likely develop even more selective isotropic etch chemistries, allowing for finer control and broader material compatibility, crucial for novel transistor designs like Gate-All-Around (GAA) devices.\n\n**2. Integration with Advanced Patterning:** As extreme ultraviolet (EUV) lithography and multi-patterning techniques become standard, the Forming Sidewall Spacers Using Isotropic Etch method will be further refined to seamlessly integrate with these ultra-fine patterning capabilities.\n\n**3. Application to 3D Stacking:** The principles of precise, damage-free material removal could be adapted for 3D integrated circuits (3D-ICs) and heterogeneous integration, enabling more compact and powerful chip packages.\n\n**4. Process Automation and AI Optimization:** Leveraging AI and machine learning for real-time process control and optimization of the isotropic etch parameters could further enhance yield and consistency. These continuous improvements ensure that Forming Sidewall Spacers Using Isotropic Etch remains a foundational technology for the future of microchip innovation and keeps pace with the demands of an ever-evolving digital world.","question":"What are the future developments expected for Forming Sidewall Spacers Using Isotropic Etch?"}],"topics":["Forming Sidewall Spacers Using Isotropic Etch","semiconductor manufacturing","isotropic etch","sidewall spacers","contact plugs","relentless","scaling","integrated"],"tech_cluster":null},"seo":{"title":"Forming Sidewall Spacers Using Isotropic Etch - Patent US-9852947","description":"Discover the groundbreaking 'Forming Sidewall Spacers Using Isotropic Etch' patent. Revolutionizing semiconductor manufacturing with precise contact plug formation and higher yields.","keywords":["Forming Sidewall Spacers Using Isotropic Etch","semiconductor manufacturing","isotropic etch","sidewall spacers","contact plugs","transistor fabrication","microchip production","etching technology","US-9852947 patent","advanced node","semiconductor innovation","precision etching","device scaling"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852947","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852947","citation_suggestion":"Patentable. \"Forming sidewall spacers using isotropic etch\" (US-9852947). https://patentable.app/patents/US-9852947","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852947","json":"https://patentable.app/api/llm-context/US-9852947","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:46:52.754Z"}