{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852950","patent":{"patent_number":"US-9852950","title":"Superimposed transistors with auto-aligned active zone of the upper transistor","assignee":null,"inventors":[],"filing_date":"2016-06-16T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"Integrated circuit equipped with at least two levels of superimposed transistors, comprising:a first transistor at a first level,a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistora second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug."},"analysis":{"summary":"The patent **Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor** introduces a revolutionary approach to integrated circuit design, enabling highly efficient vertical stacking of transistors. This innovation tackles the critical challenge of precise inter-layer alignment in 3D integrated circuits, a long-standing hurdle in semiconductor manufacturing.\n\nThe core innovation lies in a design where a first transistor on a lower level utilizes its own conductive plugs (connected to its drain, gate, and source) to automatically define and align the active zone of a second, superimposed transistor. These plugs extend through an insulating layer, and the upper transistor's active zone is formed in a semiconducting layer at their ends, with its gate strategically positioned between specific plugs. This ingenious method ensures that the upper transistor's critical operational area is inherently aligned with the lower layer's architecture, eliminating the need for complex and error-prone external alignment steps.\n\nThis technical approach significantly simplifies the fabrication process for 3D integrated circuits. By making alignment self-correcting, it reduces manufacturing complexity, improves production yields, and potentially lowers overall costs. The technology paves the way for creating microprocessors, memory chips, and other electronic components with substantially higher transistor densities and improved performance characteristics, all while consuming less power.\n\nFrom a business perspective, the Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent opens vast market opportunities in high-performance computing, artificial intelligence, mobile devices, and the Internet of Things (IoT). Companies adopting this technology can gain a significant competitive advantage by developing more powerful, compact, and energy-efficient products. This innovation is poised to accelerate the next generation of electronic devices, making sophisticated 3D ICs more economically viable and widely accessible.","layman_explanation":"In the fast-paced world of technology, every business professional knows that 'smaller, faster, cheaper' is the mantra. For decades, the engine behind this progress has been the continuous shrinking of transistors – the tiny on/off switches that make up every computer chip. However, we're reaching the physical limits of how small we can make them horizontally. The next frontier is to build upwards, stacking these transistors in three dimensions.\n\n**1. What Problem Does This Solve?**\nThe dream of '3D chips' has been around for a while, but it's been plagued by a massive manufacturing headache: **alignment**. Imagine trying to build a skyscraper where each floor's critical features must align perfectly with the one below it, down to the millimeter, or the whole building collapses. For microchips, this 'alignment problem' is exponentially harder. Even microscopic misalignments between stacked transistor layers can lead to non-functional chips, wasted production, and sky-high costs. Existing solutions often involve incredibly complex and expensive optical systems, which slow down production and still don't guarantee perfect yields. This has been a significant barrier to truly unlocking the potential of vertically integrated electronics.\n\n**2. How Does It Work?**\nThe patent **Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor** offers an ingenious solution. Instead of relying on external alignment tools for each layer, this invention makes the alignment process *self-correcting*. Think of it like this: You have a first layer of transistors. From its critical parts (like the 'in' and 'out' gates), tiny, super-precise electrical 'plugs' grow upwards through an insulating layer. Now, when you're ready to build the *second* layer of transistors directly on top, the most important part of that upper transistor – its 'active zone' where the switching happens – is actually formed *using the ends of those very plugs as its guide*. The upper transistor's gate then slots in perfectly between these same plugs.\n\nIt's akin to having a pre-drilled template for your next floor, where the supporting pillars from the floor below guide exactly where the new floor's critical components must be placed. This eliminates the guesswork and the need for external, error-prone alignment steps. The alignment is baked into the design, making the process inherently more robust and reliable.\n\n**3. Why Does This Matter?**\nThis innovation has profound implications for businesses:\n*   **Market Leadership:** Companies adopting this technology can develop chips with unprecedented transistor density, leading to significantly more powerful and compact products. This translates to a competitive edge in everything from smartphones and laptops to high-performance servers and AI accelerators.\n*   **Cost Reduction & ROI:** By simplifying the manufacturing process and drastically improving yields (fewer defective chips), production costs can be substantially reduced. This directly impacts profitability and offers a strong return on investment for semiconductor manufacturers.\n*   **New Product Opportunities:** The ability to reliably stack transistors opens doors for entirely new categories of devices – ultra-miniaturized sensors, more powerful edge computing devices, and highly integrated System-on-Chips (SoCs) that were previously unfeasible.\n*   **Energy Efficiency:** Better alignment and denser packing can also lead to shorter electrical pathways, reducing power consumption, which is critical for mobile and IoT devices.\n\n**4. What's Next?**\nThe Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent is a foundational technology. We can expect to see its principles integrated into future generations of microprocessors, memory, and specialized AI chips. Its adoption will likely accelerate the transition to advanced 3D integrated circuits, making them more common and affordable. For investors, this represents an opportunity to back companies at the forefront of semiconductor innovation, poised to capitalize on the next wave of computing advancements.","technical_analysis":"The patent **Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor** (US-9852950) presents a significant advancement in the field of 3D integrated circuit (IC) architecture and fabrication. This invention addresses one of the most persistent and challenging issues in vertical device stacking: the precise alignment of active zones between superimposed transistor layers. Traditional multi-layer fabrication often relies on highly complex and expensive lithographic techniques to achieve inter-layer registration, which can lead to cumulative errors, reduced yields, and increased manufacturing costs.\n\n**Technical Architecture:**\nThe core of this innovation lies in a vertically integrated structure comprising at least two levels of transistors. A first transistor (T1) is situated at a foundational level. Critical to this design are three electrically conductive plugs: a first plug connected to T1's drain region, a second plug connected to T1's gate, and a third plug connected to T1's source region. These plugs are formed to extend vertically upwards, passing through an insulating dielectric layer that covers T1.\n\n**Implementation Details & Auto-Alignment Mechanism:**\nAbove this insulating layer, a second transistor (T2) is fabricated. The ingenuity of this patent is in how T2's active zone is defined. A semi-conducting layer, which will form T2's channel, is arranged such that its lateral position is dictated by the precise termination points of the aforementioned plugs. Specifically, this layer is formed at one end of the plugs, directly facing the first transistor. Subsequently, T2's gate is formed, strategically positioned between the first plug (connected to T1's drain) and the third plug (connected to T1's source). This spatial relationship ensures that the active zone of T2 is inherently and automatically aligned with the underlying structure defined by T1's interconnects.\n\nThis 'auto-aligned active zone' mechanism is a major breakthrough. Instead of requiring separate, high-precision alignment steps for each superimposed layer, the invention leverages the pre-existing, accurately patterned plugs of the lower transistor as intrinsic alignment guides for the upper transistor. This process can be viewed as a form of self-assembly or self-registration at the device level, significantly reducing the critical alignment budget during fabrication.\n\n**Algorithm Specifics (Fabrication Sequence):**\n1.  **First Transistor (T1) Fabrication:** Standard CMOS processing is used to create T1 on a substrate.\n2.  **Insulating Layer Deposition:** A dielectric layer is deposited and planarized over T1.\n3.  **Plug Formation:** Vias are etched through the insulating layer to T1's drain, gate, and source. These vias are then filled with conductive material (e.g., tungsten, copper) to form the first, second, and third plugs. The precise patterning of these plugs is crucial and typically achieved with high-resolution lithography.\n4.  **Semi-conducting Layer Deposition:** A blanket layer of semiconducting material (e.g., polysilicon or an epitaxially grown silicon layer) is deposited over the plugs and insulating layer.\n5.  **Upper Transistor Active Zone Definition:** Patterning and etching techniques are used to define the active zone of T2 from the semi-conducting layer. The lateral boundaries of this active zone are designed to be self-aligned with the perimeter defined by the upper ends of the first and third plugs.\n6.  **Upper Transistor Gate Formation:** T2's gate dielectric and gate electrode are then patterned and deposited. The gate is placed between the first and third plugs, ensuring its precise alignment relative to the newly defined active zone.\n\n**Performance Characteristics and Code-level Implications:**\nThis architecture promises several performance benefits. The inherent alignment reduces parasitic overlaps, leading to lower parasitic capacitance and improved switching speeds. Furthermore, the compact vertical stacking enables shorter interconnect lengths, reducing resistance and improving signal integrity. For chip designers and engineers, this means greater flexibility in creating ultra-dense, high-performance logic and memory blocks. While there are no direct 'code-level implications' in the software sense, the invention profoundly impacts hardware architecture, enabling more complex system-on-chip (SoC) designs and advanced processor layouts that were previously limited by physical fabrication constraints. It facilitates the creation of hardware capable of accelerating AI workloads, high-frequency computing, and ultra-low-power edge devices, providing a more optimized hardware foundation for future software innovations.","business_analysis":"The patent **Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor** represents a pivotal innovation with substantial business implications across the entire semiconductor value chain and beyond. As the industry grapples with the slowing pace of Moore's Law and the increasing demand for computational power in an increasingly connected world, this technology offers a robust pathway to continued performance scaling and efficiency gains.\n\n**Market Opportunity Size:** The global semiconductor market is projected to reach over a trillion dollars in the coming years. Within this, the segment for advanced logic and memory, particularly 3D ICs, is experiencing rapid growth. This patent directly targets the core manufacturing capabilities required for these high-value segments. By enabling denser, more reliable, and cost-effective 3D integration, it unlocks market opportunities in high-performance computing (HPC), artificial intelligence (AI) accelerators, next-generation mobile processors, automotive electronics, and the burgeoning Internet of Things (IoT) sector. The ability to stack transistors efficiently translates directly into more powerful, compact, and energy-efficient chips, which are in high demand across these industries.\n\n**Competitive Advantages:** Companies that license or develop products based on Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor will gain several key competitive advantages:\n1.  **Cost Efficiency:** The auto-alignment mechanism significantly reduces the need for expensive, ultra-precise lithography steps between layers, lowering overall manufacturing costs and improving profit margins.\n2.  **Improved Yields:** Eliminating a major source of inter-layer misalignment defects directly leads to higher production yields, reducing waste and increasing profitability.\n3.  **Performance Leadership:** Denser transistor packing and optimized electrical pathways enable superior chip performance (faster speeds, lower power consumption), allowing for differentiated products.\n4.  **Time-to-Market:** Simplified manufacturing processes can accelerate product development cycles, giving early adopters a lead in launching next-generation devices.\n\n**Revenue Potential & Business Models:** This innovation can generate revenue through various business models:\n*   **Licensing:** Semiconductor IP companies can license the patent to major fabs and chip designers.\n*   **Foundry Services:** Foundries can offer advanced 3D fabrication services using this technology, attracting high-value clients.\n*   **Product Differentiation:** Chip designers (e.g., CPU, GPU, memory manufacturers) can integrate this technology into their products, commanding premium prices for enhanced performance and efficiency.\n*   **New Product Categories:** The ability to create ultra-compact, powerful chips may enable entirely new categories of electronic devices.\n\n**Strategic Positioning:** This patent strategically positions its adopters at the forefront of 3D IC technology. It addresses a fundamental roadblock to vertical scaling, allowing companies to overcome the limitations of planar scaling. This puts them in a strong position to dominate future markets where density, performance, and power efficiency are paramount. It also offers a defensive strategy against competitors still struggling with traditional 3D alignment challenges.\n\n**ROI Projections:** The return on investment for implementing or licensing this technology is potentially very high. Reductions in manufacturing costs and increased yields directly impact the bottom line. Furthermore, the ability to develop leading-edge products with superior performance can capture significant market share and drive premium pricing. For a large semiconductor manufacturer, even a few percentage points improvement in yield across high-volume production can translate into hundreds of millions of dollars in additional revenue annually. The long-term strategic value of securing a leadership position in 3D IC manufacturing, enabled by this patent, is immeasurable.","faqs":[{"answer":"Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor is a groundbreaking patent (US-9852950) that introduces an innovative architecture for building integrated circuits (ICs) with vertically stacked transistors. Traditionally, ICs are planar, meaning transistors are laid out on a flat surface. As devices get smaller, engineers are looking to stack transistors in 3D to increase density and performance.\n\nThis invention provides a solution to one of the biggest challenges in 3D stacking: precisely aligning the active components of transistors on different layers. It describes a system where the active zone of an upper transistor is automatically aligned by the electrical connections (plugs) extending from a lower transistor. This self-alignment mechanism simplifies manufacturing and improves the reliability of stacked chips.\n\nEssentially, it's a method to create denser, more powerful, and more energy-efficient microchips by making the vertical stacking process inherently more accurate and less prone to manufacturing errors. This is a significant step forward in semiconductor technology, enabling the continued miniaturization and performance enhancement of electronic devices.","question":"What is Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor?"},{"answer":"The core principle of Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor lies in its ingenious use of a lower transistor's structural elements to guide the formation of an upper transistor. First, a transistor is fabricated on a base layer. From its key regions—the drain, gate, and source—conductive plugs are formed that extend vertically upwards through an insulating layer.\n\nCrucially, when the second, upper transistor is fabricated, its 'active zone' (the area where the transistor performs its switching function) is defined in a semiconducting layer that is physically formed at the precise ends of these plugs. The gate of this upper transistor is then strategically placed between specific plugs (specifically, the plugs connected to the lower transistor's drain and source).\n\nThis design means that the upper transistor's most critical operational area is automatically aligned with the underlying structure of the lower transistor. The plugs act as inherent guides, eliminating the need for complex and error-prone external alignment steps that are typically required in multi-layer chip fabrication. This built-in precision streamlines the manufacturing process significantly.","question":"How does Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor work?"},{"answer":"The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent primarily solves the critical 'inter-layer alignment problem' in 3D integrated circuit (IC) manufacturing. As semiconductor technology pushes towards stacking transistors vertically to achieve higher densities and performance, ensuring that features on different silicon layers align perfectly becomes incredibly challenging.\n\nEven microscopic misalignments can lead to non-functional chips, reduced performance, increased power leakage, and ultimately, significant manufacturing waste and higher costs. Traditional methods for aligning these layers are complex, expensive, and a major source of defects. This invention bypasses these issues by introducing a self-alignment mechanism, making the vertical stacking of transistors much more reliable and economically viable.\n\nBy overcoming this fundamental hurdle, this technology enables the continued advancement of Moore's Law through vertical scaling, which is crucial as conventional 2D scaling approaches its physical limits. It allows for the creation of denser, more efficient, and more powerful chips without the prohibitive manufacturing complexities of prior 3D stacking techniques.","question":"What problem does Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor solve?"},{"answer":"The patent Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor (US-9852950) lists **not provided** as the inventors. The assignee for this patent is also **not provided** in the provided data. This information is typically found in the full patent document, which would detail the specific individuals and the company or institution to which the patent rights are assigned.\n\nUnderstanding the inventors and assignee is important for tracing the origins of the innovation and its potential commercialization path. However, the technical details of the invention itself, as described in the abstract and claims, clearly outline a sophisticated approach to semiconductor manufacturing, regardless of the specific origin details not provided in this summary. The innovation focuses on a structural and fabrication method for integrated circuits that significantly improves vertical transistor stacking.","question":"Who invented Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor?"},{"answer":"The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor offers several significant benefits that can revolutionize integrated circuit design and manufacturing:\n\nFirstly, it enables **significantly higher transistor density**. By making vertical stacking reliable and efficient, more transistors can be packed into a smaller physical footprint, leading to more powerful and compact chips. This is crucial for devices like smartphones, AI accelerators, and high-performance computing systems.\n\nSecondly, it leads to **improved manufacturing yields and reduced costs**. The auto-alignment mechanism eliminates a major source of defects (inter-layer misalignment), meaning more functional chips are produced from each wafer. This reduction in waste and complexity translates directly into lower production costs and faster time-to-market for advanced chips.\n\nFinally, the technology contributes to **enhanced performance and energy efficiency**. Precise alignment reduces parasitic capacitances and resistances, leading to faster switching speeds and lower power consumption. This is vital for extending battery life in mobile devices and reducing the energy footprint of data centers. Overall, this patent offers a pathway to continue the exponential growth in computing power while addressing critical manufacturing and efficiency challenges.","question":"What are the key benefits of Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor?"},{"answer":"Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor distinguishes itself from prior art in 3D integrated circuit (IC) technology primarily through its novel **auto-alignment mechanism**. Previous 3D stacking methods, such as wafer bonding or conventional monolithic 3D (M3D) approaches, typically rely on external, high-precision photolithographic alignment steps for each stacked layer.\n\nThis prior art often suffers from cumulative alignment errors, increased manufacturing complexity, high costs due to specialized equipment, and compromised yields. Each independent alignment step introduces potential inaccuracies that can lead to device failure. In contrast, this patent's innovation uses the existing, precisely defined conductive plugs of the *lower* transistor to inherently dictate the position and shape of the *upper* transistor's active zone.\n\nThis means the alignment is 'built-in' by design, rather than being an external, error-prone process. It significantly simplifies the fabrication flow, reduces the need for ultra-precise inter-layer lithography, and bypasses the limitations that have plagued prior attempts at achieving truly dense and reliable vertical transistor integration. The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor offers a more robust, cost-effective, and scalable solution for 3D IC manufacturing.","question":"How is Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor different from prior art?"},{"answer":"The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent has the potential to significantly impact a wide array of industries that rely on advanced semiconductor technology. Its ability to enable denser, more powerful, and energy-efficient chips will drive innovation across several sectors.\n\n**Consumer Electronics:** Smartphones, laptops, tablets, and wearable devices will benefit from more powerful processors, longer battery life, and more compact designs. This could lead to new form factors and capabilities.\n\n**High-Performance Computing (HPC) & Data Centers:** Supercomputers, cloud servers, and data centers will gain from higher core counts, increased memory capacity, and improved energy efficiency, crucial for handling massive data loads and complex computations.\n\n**Artificial Intelligence (AI) & Machine Learning:** Specialized AI accelerators for training and inference will become significantly more powerful and efficient, enabling breakthroughs in autonomous systems, natural language processing, computer vision, and edge AI applications.\n\n**Automotive:** Advanced driver-assistance systems (ADAS) and autonomous vehicles require immense processing power in a compact, reliable form factor, which this technology can provide. It will also enhance in-car infotainment and connectivity.\n\n**Internet of Things (IoT):** Billions of connected devices will become smarter, more capable, and operate longer on battery power, expanding the scope and utility of the IoT ecosystem. From smart homes to industrial sensors, the impact will be pervasive. In essence, any industry driven by advanced electronics will see transformative benefits from this technology.","question":"What industries will Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor impact?"},{"answer":"The patent **Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor** (US-9852950) was filed on **2016-06-16**. This date marks when the application for the patent was officially submitted to the patent office, initiating the examination process.\n\nIt was subsequently published on **2017-12-26**. The publication date is when the patent application officially becomes publicly available, allowing others to review its details and claims. While the specific grant date (when the patent is officially issued) is not explicitly provided in the initial data, the publication date indicates its public disclosure and the progression of the patenting process.\n\nThese dates are important for understanding the timeline of the invention's development and its position within the broader landscape of semiconductor innovation. The period between filing and publication allows for examination by patent authorities and provides a snapshot of the technological advancements being made at that time.","question":"When was Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor filed/granted?"},{"answer":"The commercial applications of Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor are vast and span across numerous high-tech sectors, driven by the demand for more powerful, compact, and energy-efficient electronic components.\n\n**High-Performance Processors:** This technology can lead to the development of next-generation CPUs, GPUs, and specialized accelerators with significantly higher core counts and processing capabilities, essential for cloud computing, AI, and scientific research. Companies can offer differentiated products with superior performance metrics.\n\n**Advanced Memory Solutions:** It can be applied to create denser and faster memory chips (e.g., 3D NAND, HBM - High Bandwidth Memory), crucial for improving data throughput and reducing latency in data-intensive applications. This enables more efficient data centers and powerful personal devices.\n\n**Compact Mobile Devices:** The ability to pack more functionality into smaller spaces with lower power consumption makes it ideal for smartphones, wearables, and other portable electronics, allowing for thinner devices with extended battery life and enhanced features.\n\n**IoT and Edge Computing:** For the burgeoning Internet of Things, this innovation means smarter sensors, more capable edge devices, and longer-lasting battery-powered gadgets that can perform complex tasks locally without constant cloud connectivity. The reduced manufacturing cost due to improved yields also makes these advanced components more accessible for mass-market IoT deployment. Overall, this patent provides a foundational technology for a future where sophisticated electronics are ubiquitous and highly efficient.","question":"What are the commercial applications of Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor?"},{"answer":"The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent lays a robust foundation for exciting future developments in semiconductor technology. One primary expectation is the **extension to multiple superimposed layers**. While the patent describes at least two levels, the auto-alignment principle is inherently scalable, potentially enabling monolithic 3D ICs with many more active layers, leading to unprecedented transistor densities.\n\nFurther developments will likely focus on **integration with novel materials and device architectures**. Researchers may explore incorporating high-mobility channel materials for the upper transistors, or integrating different types of devices (e.g., logic and memory) within the stacked structure. This could lead to highly specialized heterogeneous integration, optimizing performance for specific workloads like AI.\n\nAnother key area is **advanced thermal management**. As transistor density increases in 3D stacks, heat dissipation becomes a critical challenge. Future innovations will likely combine this auto-alignment technology with advanced cooling solutions to ensure optimal performance and reliability. The Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor represents a foundational shift, and its principles are expected to be refined and expanded upon to create the next generation of truly high-performance, energy-efficient, and compact electronic systems across various applications.","question":"What are the future developments expected for Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor?"}],"topics":["Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor","patent US-9852950","3D integrated circuits","vertical transistor stacking","auto-alignment technology","semiconductor","industry","critical"],"tech_cluster":null},"seo":{"title":"Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor - Patent US-9852950","description":"Discover the groundbreaking Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor patent, enabling self-aligned 3D chip stacking for higher density and efficiency.","keywords":["Superimposed Transistors with Auto-aligned Active Zone of the Upper Transistor","patent US-9852950","3D integrated circuits","vertical transistor stacking","auto-alignment technology","semiconductor innovation","chip manufacturing","high-density transistors","integrated circuit design","transistor scaling","future of electronics"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852950","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852950","citation_suggestion":"Patentable. \"Superimposed transistors with auto-aligned active zone of the upper transistor\" (US-9852950). https://patentable.app/patents/US-9852950","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852950","json":"https://patentable.app/api/llm-context/US-9852950","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:27:46.217Z"}