{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852973","patent":{"patent_number":"US-9852973","title":"Manufacturing method of chip package and package substrate","assignee":null,"inventors":[],"filing_date":"2017-03-10T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on the first circuit layer and the carrier. A dielectric layer is formed on the carrier to embed the passive component and the first circuit layer in the dielectric layer. A second circuit layer is formed on the dielectric layer. The carrier is removed from the dielectric layer. A manufacturing method of a chip package is also provided."},"analysis":{"summary":"The 'Manufacturing Method of Chip Package and Package Substrate' patent (US-9852973) introduces a groundbreaking approach to fabricating electronic package substrates, fundamentally enhancing the integration and performance of chip packages. At its core, this innovation solves the problem of limited miniaturization and potential reliability issues associated with traditionally surface-mounted passive components.\n\nThe key technical approach involves a multi-step manufacturing process. First, a foundational circuit layer is formed on a temporary carrier. Crucially, passive components—such as resistors, capacitors, and inductors—are then precisely disposed on this initial circuit layer and the carrier. Following this, a dielectric layer is meticulously formed over these elements, effectively embedding both the passive components and the first circuit layer within an insulating matrix. A second circuit layer is subsequently fabricated on the surface of this new dielectric layer, establishing further electrical connections. The final step involves the removal of the temporary carrier, resulting in a standalone, highly integrated package substrate.\n\nFrom a business perspective, this method offers significant value. It enables the creation of significantly smaller, more compact chip packages, which is vital for the continued miniaturization of electronic devices across various sectors, including consumer electronics, IoT, and medical technology. By embedding components, the invention enhances the overall reliability and durability of the package by protecting sensitive parts from environmental stress and mechanical damage. Furthermore, shorter electrical pathways lead to improved electrical performance, such as reduced signal noise and better power efficiency, translating into superior end-product performance and potentially lower power consumption.\n\nThe market opportunity for this technology is substantial. Industries demanding high-density integration, robust performance, and extended product lifespans stand to benefit immensely. This approach provides a competitive advantage for manufacturers who adopt it, allowing them to develop next-generation products that surpass current limitations. It opens doors for new product categories requiring ultra-compact and highly reliable electronic modules, positioning early adopters at the forefront of innovation in the global semiconductor market.","layman_explanation":"### What Problem Does This Solve?\nImagine trying to make a very thin sandwich, but all your ingredients—like cheese, lettuce, and tomatoes—are sitting *on top* of the bread. It gets bulky, things can slide off, and it's hard to make it really compact. In the world of electronics, this is similar to how many tiny helper parts, called 'passive components' (like miniature resistors or capacitors), are added to a computer chip's base, or 'package substrate.' These components are typically surface-mounted, meaning they sit on the surface. This approach creates several problems: it limits how small you can make the overall chip package, it can make the chip more vulnerable to physical damage, and the connections between parts are longer, which can slow things down or waste power.\n\nThis patent, the 'Manufacturing Method of Chip Package and Package Substrate,' directly addresses these issues. It's about finding a smarter, more integrated way to build the 'sandwich' so it's much thinner, stronger, and performs better, paving the way for truly miniature and reliable electronic devices.\n\n### How Does It Work?\nThink of this innovation as building that sandwich in layers, but baking the ingredients *into* the bread itself. The process starts by creating a first electrical pathway (a 'circuit layer') on a temporary base, similar to a baking sheet. Then, those tiny passive components are carefully placed onto this first layer. Here's the clever part: instead of leaving them exposed, a special insulating material (a 'dielectric layer') is poured over everything, completely embedding the components and the first circuit layer. This is like baking the cheese and lettuce *into* the middle layer of your bread. Once that layer is set, another electrical pathway (a 'second circuit layer') is added on top. Finally, the temporary baking sheet is removed, leaving behind a compact, multi-layered chip package where all the essential helper components are safely and efficiently integrated inside. This embedded design means everything is tightly packed and protected, with very short, direct connections.\n\n### Why Does This Matter?\nThis method has profound implications for the business world. Firstly, it enables unprecedented miniaturization. For industries like consumer electronics (think smartphones, smartwatches), medical devices (e.g., tiny implantables), and the Internet of Things (IoT) where size is critical, this means products can become significantly smaller, lighter, and more aesthetically pleasing. Secondly, embedding components dramatically improves reliability. Encapsulated within the protective dielectric layer, these sensitive parts are less susceptible to environmental factors like moisture, dust, and physical shocks, leading to longer product lifespans and reducing costly warranty claims. Thirdly, the shorter electrical pathways improve performance—chips can operate faster with less power loss, which translates into more efficient and powerful end products. This innovation provides a significant competitive edge for companies that adopt it, allowing them to create differentiated products that outperform and outlast existing solutions. It's about delivering more value in a smaller, more robust package, potentially opening up entirely new markets and applications.\n\n### What's Next?\nThis technology is a foundational step towards even more advanced electronic integration. We can expect to see its principles applied in future developments like highly integrated 'system-in-package' (SiP) solutions, where entire subsystems are built into a single, tiny module. It will accelerate the trend of 'ubiquitous computing,' enabling powerful electronics to be seamlessly integrated into everyday objects and environments. Businesses investing in or licensing this technology will be well-positioned to lead the charge in designing the next generation of compact, high-performance, and ultra-reliable devices, driving innovation across multiple sectors and capturing significant market share in an increasingly miniaturized world.","technical_analysis":"The 'Manufacturing Method of Chip Package and Package Substrate' patent (US-9852973) outlines a sophisticated process for constructing advanced package substrates, with a particular focus on the integration of passive components. This invention represents a significant technical advancement in the field of heterogeneous integration and advanced semiconductor packaging, addressing critical challenges related to miniaturization, signal integrity, and reliability.\n\n**Technical Architecture and Process Flow:**\nThe core of this method revolves around a sequential build-up process on a sacrificial carrier. The first step involves **forming a first circuit layer on a carrier**. This typically entails depositing a conductive material (e.g., copper, aluminum) onto a temporary substrate, followed by photolithography and etching to define the initial electrical traces and pads. The carrier itself is often a rigid material chosen for its ease of handling and subsequent removal properties, such as glass or a silicon wafer with a release layer.\n\nNext, **passive components are disposed on the first circuit layer and the carrier**. This is a crucial step requiring high-precision component placement, often utilizing automated pick-and-place systems. These passive components (e.g., surface-mount resistors, capacitors, inductors) are interconnected to the first circuit layer using standard bonding techniques like reflow soldering or conductive epoxies. The strategic placement ensures optimal electrical performance and prepares them for embedding.\n\nFollowing component placement, a **dielectric layer is formed on the carrier to embed the passive component and the first circuit layer**. This dielectric material, often a polymer like epoxy resin or polyimide, is applied through processes such as spin coating, lamination, or molding. The material must fully encapsulate the components and circuit layer, providing electrical insulation, mechanical support, and protection. The curing of this dielectric layer is critical to ensure its structural integrity and electrical properties.\n\nSubsequently, a **second circuit layer is formed on the dielectric layer**. This involves standard thin-film processing techniques, including deposition of conductive material, photolithography, and etching, to create additional interconnects, power planes, and pads. Vias are typically formed through the dielectric layer to establish electrical connections between the first and second circuit layers, as well as to the embedded passive components.\n\nFinally, the **carrier is removed from the dielectric layer**. This delamination step is often performed chemically (e.g., selective etching of a release layer) or mechanically, leaving behind the freestanding package substrate with integrated passive components. The successful removal without damaging the delicate substrate is a testament to the precise material selection and process control.\n\n**Implementation Details and Algorithm Specifics:**\nWhile the patent abstract doesn't detail specific algorithms, the underlying principles suggest optimization for several parameters. Precision in component placement (sub-micron accuracy) and alignment of circuit layers are paramount. The choice of dielectric material impacts insulation resistance, dielectric constant, loss tangent, and thermal expansion coefficient – all critical for high-frequency performance and thermal cycling reliability. The etching processes for circuit layers and carrier removal must be highly selective to prevent damage to adjacent layers. The 'algorithm' here is less computational and more a sequence of precisely controlled physical and chemical manufacturing steps, optimized for yield and performance.\n\n**Integration Patterns and Performance Characteristics:**\nThis method facilitates advanced 2.5D and 3D integration patterns by allowing for a higher density of components within a planar substrate. It enables the creation of highly compact power delivery networks (PDNs) with embedded decoupling capacitors, crucial for reducing voltage noise and improving transient response in high-speed digital circuits. The shorter interconnects afforded by embedding components significantly reduce parasitic inductance and capacitance, leading to improved signal integrity, higher operating frequencies, and lower power dissipation compared to surface-mounted counterparts. Thermal management is also enhanced, as the dielectric layer can act as a heat spreader, and the compact design allows for more efficient heat removal strategies. This approach is particularly beneficial for RF modules, memory packages, and system-in-package (SiP) solutions where space and performance are at a premium.\n\n**Code-level Implications:**\nWhile this patent is hardware-centric, its implications for software and firmware development are indirect but substantial. By enabling smaller, more powerful, and reliable hardware, it allows software engineers to develop more complex, feature-rich applications for compact devices. The improved electrical performance means software can run faster and more stably. For embedded systems, the enhanced reliability translates to fewer hardware failures, simplifying software debugging and maintenance. Developers working on IoT, AI at the edge, or high-performance computing in constrained form factors will benefit from the robust foundation provided by this technology, allowing them to push computational boundaries within miniaturized systems.","business_analysis":"The 'Manufacturing Method of Chip Package and Package Substrate' patent (US-9852973) presents a compelling business opportunity by addressing fundamental limitations in current electronic packaging. Its core innovation—embedding passive components directly into package substrates—unlocks significant market potential across several high-growth industries.\n\n**Market Opportunity Size:**\nThe global semiconductor packaging market is projected to reach hundreds of billions of dollars in the coming years, driven by relentless demand for smaller, faster, and more integrated electronic devices. Within this vast market, advanced packaging solutions, particularly those enabling high-density integration and enhanced reliability, command a premium. This patent positions itself squarely within the high-value segment of this market, targeting applications in consumer electronics (smartphones, wearables), automotive (ADAS, infotainment), medical devices (implantables, diagnostics), aerospace, and IoT, all of which prioritize miniaturization, performance, and durability. The market for embedded passive components alone is growing steadily, indicating a clear demand for the technology this invention enables.\n\n**Competitive Advantages:**\nThis invention offers several distinct competitive advantages. Firstly, it provides a superior approach to miniaturization, allowing for significantly smaller package footprints compared to traditional surface-mount technologies. This directly translates into thinner, lighter, and more compact end products, a critical differentiator in consumer markets. Secondly, by encapsulating passive components within a dielectric layer, the technology dramatically enhances the reliability and robustness of chip packages, reducing susceptibility to mechanical stress, moisture, and thermal cycling. This leads to longer product lifespans and reduced warranty costs for manufacturers. Thirdly, the shorter electrical pathways inherent in embedded designs result in improved electrical performance (e.g., better signal integrity, lower power loss, higher operating frequencies), giving products a performance edge. Finally, streamlining the manufacturing process by integrating components at the substrate level can potentially lead to cost efficiencies in high-volume production, despite initial investment in specialized equipment.\n\n**Revenue Potential and Business Models:**\nRevenue potential for this technology is multi-faceted. It could be monetized through licensing agreements with major semiconductor manufacturers, foundries, and integrated device manufacturers (IDMs). Alternatively, a company could establish itself as a specialized provider of advanced package substrates utilizing this method, offering fabrication services to chip designers. The improved performance and reliability could command higher average selling prices (ASPs) for components or modules incorporating this technology. Business models could include: (1) **Technology Licensing:** Offering IP licenses to major players for integration into their manufacturing lines. (2) **Foundry Services:** Operating as a dedicated advanced packaging foundry. (3) **Product Enhancement:** Integrating the method into proprietary chip packages or modules to create differentiated high-value products.\n\n**Strategic Positioning:**\nCompanies adopting this patent can strategically position themselves as leaders in next-generation electronic packaging. This technology enables the development of products that are currently challenging or impossible to achieve with existing methods. It allows for differentiation in markets driven by form factor and ruggedness. Furthermore, it supports the trend towards heterogeneous integration, where diverse functionalities are combined in a single package, offering a pathway to highly integrated system-in-package (SiP) solutions.\n\n**ROI Projections:**\nWhile specific ROI projections depend on implementation scale and market adoption, the benefits are clear. Reduced product size can open new market segments. Enhanced reliability leads to lower field failures and improved brand reputation. Superior electrical performance enables higher-value applications. Companies investing in this technology could see returns through increased market share, premium pricing for advanced products, reduced manufacturing complexity (in the long run), and significant cost savings from improved product quality and longevity. The ability to create truly innovative products that meet evolving consumer and industrial demands represents a strong long-term ROI potential.","faqs":[{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' (US-9852973) is a patented innovation in semiconductor manufacturing that describes a novel process for fabricating package substrates. Unlike traditional methods where passive components are surface-mounted, this invention allows for these crucial components (like resistors, capacitors, and inductors) to be embedded directly within the layers of the substrate itself. This leads to a more compact, robust, and electrically efficient chip package.\n\nThe method involves a sequential build-up process: first, a circuit layer is formed on a temporary carrier. Then, passive components are precisely placed on this layer. A dielectric (insulating) layer is subsequently formed to completely encapsulate these components and the initial circuit. Another circuit layer is then added on top, and finally, the temporary carrier is removed, yielding the finished package substrate with integrated components.\n\nThis technology is designed to overcome limitations of conventional packaging, offering significant advantages in miniaturization, performance, and reliability for advanced electronic devices. It represents a foundational shift in how chip packages are designed and manufactured, moving towards higher integration densities.","question":"What is the 'Manufacturing Method of Chip Package and Package Substrate'?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' employs a multi-step, layered approach to integrate passive components directly into the package substrate. The process begins by preparing a temporary carrier, onto which a first circuit layer is formed. This layer establishes the initial electrical pathways.\n\nNext, passive components are accurately positioned on this first circuit layer and the carrier. These components are then encapsulated by forming a dielectric layer over them. This dielectric material acts as an insulator and provides mechanical protection, effectively embedding the components and the first circuit layer within the substrate structure. Following this, a second circuit layer is fabricated on the surface of the dielectric layer, creating further interconnections.\n\nFinally, the temporary carrier is removed, leaving behind a standalone package substrate with the passive components seamlessly integrated within its layers. This innovative sequence ensures that components are protected, electrical connections are shortened, and the overall package is significantly more compact and durable than those produced by traditional surface-mounting techniques.","question":"How does the 'Manufacturing Method of Chip Package and Package Substrate' work?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' primarily solves critical problems associated with traditional chip packaging, particularly the limitations imposed by surface-mounted passive components. These problems include:\n\n1.  **Limited Miniaturization:** Surface-mounted components occupy significant space, hindering the ability to create smaller, thinner electronic devices.\n2.  **Compromised Electrical Performance:** Longer electrical pathways between surface-mounted components and active chips can lead to increased parasitic inductance and capacitance, signal integrity issues, and higher power consumption.\n3.  **Reduced Reliability:** Exposed passive components are vulnerable to physical damage, mechanical stress, and environmental factors like moisture and dust, leading to shorter device lifespans and potential failures.\n\nBy enabling the embedding of passive components directly into the substrate, this invention overcomes these challenges, paving the way for ultra-compact, high-performance, and robust electronic devices. This is crucial for advancing technologies in consumer electronics, IoT, and medical devices.","question":"What problem does the 'Manufacturing Method of Chip Package and Package Substrate' solve?"},{"answer":"The patent for the 'Manufacturing Method of Chip Package and Package Substrate' (US-9852973) does not list specific inventors or an assignee in the provided data. This information is typically found in the full patent document, which would detail the individuals or entity (company) responsible for the invention.\n\nPatent filings are often the result of extensive research and development efforts by teams of engineers and scientists within large technology companies or research institutions. These innovators contribute their expertise in materials science, electrical engineering, and manufacturing processes to develop groundbreaking solutions like this one. While the immediate data doesn't specify the inventors, the technical depth of the 'Manufacturing Method of Chip Package and Package Substrate' suggests a collaborative effort by experts in advanced semiconductor packaging.","question":"Who invented the 'Manufacturing Method of Chip Package and Package Substrate'?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' offers several transformative benefits for the electronics industry:\n\n1.  **Enhanced Miniaturization:** By embedding passive components, the overall package footprint and thickness are significantly reduced, enabling the creation of smaller, lighter, and more compact electronic devices crucial for modern gadgets and IoT applications.\n2.  **Superior Electrical Performance:** Shorter electrical pathways between active and passive components lead to lower parasitic inductance and capacitance, improved signal integrity, reduced electromagnetic interference, and better power delivery. This translates to faster operating speeds and increased power efficiency.\n3.  **Increased Reliability and Durability:** The complete encapsulation of components within a protective dielectric layer shields them from physical damage, moisture, and thermal stress, dramatically extending the lifespan and robustness of the chip package.\n4.  **Higher Integration Density:** This method facilitates the integration of more components into a given area, paving the way for advanced System-in-Package (SiP) solutions and heterogeneous integration, leading to more functional and complex devices in smaller form factors. These benefits drive innovation across diverse electronic applications.","question":"What are the key benefits of the 'Manufacturing Method of Chip Package and Package Substrate'?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' fundamentally differentiates itself from prior art, particularly traditional Surface Mount Technology (SMT), by enabling the direct embedding of passive components within the substrate's layers during its fabrication. In SMT, components are soldered onto the surface, leading to larger package sizes, longer electrical connections, and exposed components vulnerable to damage. While some prior art involves Integrated Passive Devices (IPDs) or embedding in larger PCBs, this invention focuses on precise, high-density embedding directly within the fine-pitch structure of the chip package substrate itself.\n\nKey distinctions include: (1) **Integration Level:** It integrates components *within* the substrate build-up, not just on its surface or as separate pre-fabricated modules. (2) **Protection:** The complete encapsulation provides superior physical and environmental protection compared to exposed components. (3) **Performance Optimization:** The method is optimized for shorter interconnections, leading to better electrical performance than most surface-mounted solutions. These unique attributes allow the 'Manufacturing Method of Chip Package and Package Substrate' to overcome limitations in miniaturization, performance, and reliability that persist with conventional and even some advanced packaging techniques.","question":"How is the 'Manufacturing Method of Chip Package and Package Substrate' different from prior art?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' is poised to impact a wide array of industries that rely on advanced electronic components. Its ability to create smaller, faster, and more reliable chip packages makes it particularly relevant for:\n\n1.  **Consumer Electronics:** Enabling the next generation of ultra-thin smartphones, smartwatches, augmented reality (AR) glasses, and other portable devices that demand high performance in compact form factors.\n2.  **Internet of Things (IoT):** Facilitating the development of miniature, robust, and low-power sensors and modules that can be seamlessly integrated into smart homes, industrial monitoring, and environmental sensing applications.\n3.  **Automotive:** Supporting advanced driver-assistance systems (ADAS), in-vehicle infotainment, and autonomous driving platforms with more compact, durable, and high-performance electronic control units (ECUs) capable of operating in harsh conditions.\n4.  **Medical Devices:** Revolutionizing implantable devices, wearable health monitors, and diagnostic equipment by allowing for smaller, more reliable, and less invasive designs.\n5.  **Aerospace and Defense:** Providing robust and compact electronic modules for avionics, satellites, and defense systems where space, weight, and reliability are paramount. This invention is a foundational technology for future electronic innovation across these critical sectors.","question":"What industries will the 'Manufacturing Method of Chip Package and Package Substrate' impact?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' patent, identified by the number US-9852973, was filed on **March 10, 2017**. Following the examination process, it was subsequently published on **December 26, 2017**.\n\nThe filing date marks the official submission of the invention to the patent office, establishing its priority date. The publication date signifies when the patent application, or in this case, the granted patent, became publicly accessible. This timeframe indicates a relatively swift examination process, highlighting the novelty and potential significance of the 'Manufacturing Method of Chip Package and Package Substrate' in the field of advanced semiconductor packaging. Such rapid progression underscores the urgency and importance of innovations that address critical needs in electronics manufacturing.","question":"When was the 'Manufacturing Method of Chip Package and Package Substrate' filed/granted?"},{"answer":"The commercial applications of the 'Manufacturing Method of Chip Package and Package Substrate' are extensive, driven by its ability to deliver superior performance in a smaller, more reliable package. Key applications include:\n\n1.  **High-Density Modules for Mobile Devices:** Manufacturing advanced System-in-Package (SiP) modules for smartphones, tablets, and wearables, enabling thinner designs, longer battery life, and enhanced processing capabilities.\n2.  **Miniature IoT Nodes:** Producing highly integrated, robust components for tiny sensors and communication modules used in smart cities, industrial IoT, and environmental monitoring.\n3.  **Automotive Electronics:** Creating durable and compact electronic control units (ECUs) for advanced driver-assistance systems (ADAS), electric vehicle power electronics, and autonomous driving platforms.\n4.  **Medical Implants and Wearables:** Developing smaller, more reliable, and biocompatible electronic packages for pacemakers, continuous glucose monitors, and other critical medical devices.\n5.  **High-Frequency RF Modules:** Improving the performance of 5G and Wi-Fi modules by reducing parasitic losses and enhancing signal integrity through shorter, embedded interconnections.\n\nThese applications leverage the core benefits of the 'Manufacturing Method of Chip Package and Package Substrate' to meet stringent market demands for miniaturization, performance, and reliability across various sectors.","question":"What are the commercial applications of the 'Manufacturing Method of Chip Package and Package Substrate'?"},{"answer":"The 'Manufacturing Method of Chip Package and Package Substrate' lays a robust foundation for numerous future developments in advanced semiconductor packaging. We can anticipate several key evolutionary paths for this technology:\n\n1.  **Integration of Active Components:** Future iterations may extend the embedding concept to include active semiconductor dies alongside passive components, leading to even more compact and functional System-in-Package (SiP) solutions or 3D heterogeneous integration.\n2.  **Advanced Material Science:** Research will likely focus on developing new dielectric materials with even lower dielectric constants, higher thermal conductivity, and enhanced mechanical properties to push performance boundaries further and improve thermal management for the 'Manufacturing Method of Chip Package and Package Substrate'.\n3.  **Wafer-Level Packaging (WLP):** The principles of this method could be adapted for wafer-level processing, enabling the simultaneous manufacturing of thousands of package substrates on a single wafer, significantly reducing costs and increasing throughput.\n4.  **AI and Machine Learning Optimization:** AI could be employed to optimize the placement of embedded components, the design of circuit layers, and the control of manufacturing processes to maximize yield, performance, and reliability. These advancements will solidify the 'Manufacturing Method of Chip Package and Package Substrate' as a cornerstone technology for future electronics, enabling unprecedented levels of integration and performance.","question":"What are the future developments expected for the 'Manufacturing Method of Chip Package and Package Substrate'?"}],"topics":["Manufacturing Method of Chip Package and Package Substrate","chip package manufacturing","package substrate","embedded passive components","semiconductor packaging","relentless","march","towards"],"tech_cluster":null},"seo":{"title":"Manufacturing Method of Chip Package and Package Substrate - Patent US-9852973","description":"Discover how the Manufacturing Method of Chip Package and Package Substrate revolutionizes electronics packaging with embedded components. Achieve smaller, faster, and more reliable devices. Full analysis of US-9852973.","keywords":["Manufacturing Method of Chip Package and Package Substrate","chip package manufacturing","package substrate","embedded passive components","semiconductor packaging","electronics miniaturization","dielectric layer","advanced packaging","system-in-package","high-density integration","patent US-9852973"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852973","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852973","citation_suggestion":"Patentable. \"Manufacturing method of chip package and package substrate\" (US-9852973). https://patentable.app/patents/US-9852973","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852973","json":"https://patentable.app/api/llm-context/US-9852973","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:14:17.167Z"}