{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852977","patent":{"patent_number":"US-9852977","title":"Package substrate","assignee":null,"inventors":[],"filing_date":"2016-11-15T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":16,"abstract":"This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer."},"analysis":{"summary":"The Package Substrate patent (US-9852977) introduces a sophisticated multi-layered electronic package designed to significantly enhance the performance, density, and reliability of integrated circuits. At its core, this innovation provides a foundational structure comprising a rigid dielectric material layer, a first wiring layer with precisely formed metal wires, and a crucial first flexible dielectric material layer positioned atop the wiring layer. This unique combination addresses critical limitations inherent in traditional, purely rigid substrates.\n\nThe primary problem this technology solves is the increasing difficulty of maintaining signal integrity, managing thermal stress, and ensuring mechanical robustness in ever-smaller and more powerful electronic devices. Conventional substrates often lead to signal degradation at high frequencies, are prone to cracking under thermal cycling, and struggle to accommodate the ultra-fine interconnects required by modern chip architectures.\n\nThe Package Substrate's key technical approach lies in its hybrid material integration. The rigid dielectric layer provides structural stability and a robust platform for component attachment. The first wiring layer ensures efficient electrical pathways. The flexible dielectric layer is the game-changer, offering stress relief against thermal expansion mismatches, enabling finer pitch wiring, and improving overall package durability. This layered design optimizes electrical performance by reducing parasitic effects and enhances mechanical resilience.\n\nFrom a business perspective, this invention offers substantial value. It enables the development of next-generation high-performance computing, advanced communication systems (e.g., 5G/6G), and miniaturized IoT devices that demand superior reliability and efficiency. Companies adopting this technology can achieve higher integration densities, reduce manufacturing defects related to package stress, and deliver products with extended operational lifespans. This translates to competitive advantages in key growth markets.\n\nThe market opportunity for the Package Substrate is vast, spanning across consumer electronics, automotive, aerospace, industrial, and medical sectors. As the demand for more powerful, compact, and reliable electronics continues to grow, this foundational packaging technology offers a scalable and robust solution, positioning itself as a critical enabler for future technological advancements and an attractive prospect for investment.","layman_explanation":"### 1. What Problem Does This Solve?\n\nImagine the intricate circuit board inside your smartphone or laptop. This board, specifically the 'package substrate' part, is the unsung hero that connects the main computer chip (the 'brain') to the rest of the device. For years, these substrates have been made from rigid materials. While strong, this rigidity creates significant challenges as chips become incredibly tiny and powerful.\n\nThe core problem is twofold: **performance and reliability**. When chips process information at lightning speed, electrical signals can degrade or interfere with each other on conventional rigid substrates, leading to slower performance or errors. Furthermore, the constant heating and cooling cycles that every electronic device goes through cause materials to expand and contract. A rigid substrate can't flex, so these thermal stresses often lead to microscopic cracks or detachments, significantly shortening the device's lifespan. Existing solutions often involve trade-offs: either sacrificing speed for durability or vice-versa, leaving a gap for truly high-performance, long-lasting electronics.\n\n### 2. How Does It Work?\n\nThe Package Substrate patent (US-9852977) introduces a clever solution by combining the best attributes of rigid and flexible materials. Think of it like building a road for tiny, super-fast cars (electrical signals).\n\nFirst, there's a **strong, rigid base layer**, much like a sturdy concrete foundation. This provides the essential structural support. On top of this rigid base, incredibly fine **metal wires** are laid out, acting like precision-engineered highways for the electrical signals. These wires are designed to carry data with minimal interference.\n\nNow, here's the innovation: a **flexible, protective layer** is placed directly over these wires. Imagine this as a high-tech, slightly elastic membrane. This flexible layer serves multiple critical purposes: it insulates the wires, allows for even more intricate routing of signals in very tight spaces, and most importantly, it acts as a shock absorber. When the chip heats up and expands, or cools down and contracts, this flexible layer gently stretches and contracts with it, preventing the damaging stresses that occur in purely rigid systems. It's like having a resilient, adaptive cushion that protects the delicate wiring and connections underneath.\n\n### 3. Why Does This Matter?\n\nThis innovation has profound implications for the business world and the broader electronics market. By solving the performance and reliability challenges of traditional substrates, the Package Substrate enables a new generation of electronic devices that are not just faster, but also significantly more durable and capable of higher integration. This translates into several key advantages:\n\n*   **Market Leadership:** Companies adopting this technology can create differentiated products that outperform competitors, capturing market share in high-growth segments like AI hardware, 5G/6G devices, autonomous vehicle systems, and advanced medical equipment.\n*   **Reduced Costs & Enhanced Reputation:** Improved reliability means fewer product failures, lower warranty claims, and enhanced customer satisfaction. This directly impacts a company's bottom line and strengthens its brand reputation.\n*   **Innovation Catalyst:** The ability to pack more functionality into smaller, more robust packages opens doors for entirely new product categories and miniaturized solutions, fostering rapid innovation across various industries. Imagine thinner, lighter, yet more powerful devices with extended lifespans.\n*   **Investment Opportunity:** For investors, this patent represents a foundational technology addressing a universal need in a rapidly expanding market. Its potential for widespread adoption across diverse applications makes it an attractive investment in the underlying infrastructure of modern electronics.\n\n### 4. What's Next?\n\nThe Package Substrate is poised to become a standard in high-performance and high-reliability electronic packaging. We can expect to see this technology integrated into next-generation processors, memory modules, and specialized sensors within the next few years. Its modular nature also suggests future applications in advanced 3D packaging and heterogeneous integration, where different types of chips are combined into a single, compact unit. This innovation sets a new benchmark for electronic foundations, driving a wave of progress in how we design and experience technology.","technical_analysis":"The patent US-9852977, known as the Package Substrate, details a significant advancement in electronic packaging technology. This invention introduces a novel multi-layered architecture designed to overcome inherent limitations in conventional package substrates, particularly concerning signal integrity, thermal management, and mechanical reliability in high-performance electronic devices. The core of this technology lies in its intelligent integration of distinct material properties within a single substrate structure.\n\n**Technical Architecture and Material Composition:**\nThe Package Substrate is fundamentally composed of three primary, interconnected layers: a rigid dielectric material layer, a first wiring layer, and a first flexible dielectric material layer. The rigid dielectric material layer serves as the foundational structural element, providing mechanical stability and a robust base for subsequent fabrication processes and component attachment. Typical materials for this layer include epoxy resins (e.g., BT resin), polyimide, or ceramic-filled laminates, chosen for their mechanical strength, thermal stability, and low coefficient of thermal expansion (CTE) relative to silicon dies.\n\nFormed directly on this rigid dielectric layer is the first wiring layer. This layer consists of at least one precisely patterned metal wire, typically copper, which forms the electrical pathways for signals, power, and ground. The fabrication of this layer involves advanced photolithography and etching techniques to achieve fine line widths and spaces, critical for high-density interconnects (HDIs). The design of these wires, including their geometry, spacing, and routing, is paramount for minimizing parasitic capacitance and inductance, thereby ensuring signal integrity at high operating frequencies.\n\nCrucially, a first flexible dielectric material layer is formed on the first wiring layer. This flexible layer, often composed of materials like polyimide (PI), liquid crystal polymer (LCP), or flexible epoxy resins, represents a key innovation. Its primary functions are multifaceted: it provides an additional insulating layer for subsequent wiring, offers significant stress relief against thermal expansion mismatches between the silicon die and the rigid substrate, and enables highly complex, fine-pitch interconnect routing that might be challenging or impossible on a purely rigid surface.\n\n**Implementation Details and Performance Characteristics:**\nThe integration of the flexible dielectric layer directly over the wiring on the rigid base offers distinct advantages. Electrically, the flexible material can be chosen for its superior dielectric constant (Dk) and dissipation factor (Df) characteristics, which are critical for high-frequency signal transmission. This helps reduce signal loss, crosstalk, and impedance discontinuities, leading to cleaner signals and faster data rates for applications like 5G/6G, PCIe Gen5/6, and DDR5/6 memory interfaces. The ability to create more sophisticated routing patterns within the flexible layer also allows for optimized ground and power planes, further enhancing electrical performance.\n\nMechanically, the flexible layer acts as a compliant buffer. During thermal cycling, the CTE mismatch between the silicon chip and the rigid substrate can induce significant stress, leading to solder joint fatigue, delamination, and package cracking. The inherent elasticity of the flexible layer absorbs and distributes these stresses more effectively, dramatically improving the long-term reliability and operational lifespan of the packaged device. This is particularly vital for automotive, industrial, and aerospace electronics where extreme temperature variations are common.\n\n**Integration Patterns and Code-Level Implications:**\nWhile this patent primarily describes a hardware architecture, its implications for software and firmware are indirect but profound. A more reliable and higher-performing Package Substrate enables the development of more complex and faster integrated circuits. This means software developers can leverage higher clock speeds, increased core counts, and faster memory access, potentially leading to more sophisticated algorithms, real-time processing capabilities, and larger data throughputs. For instance, in AI/ML accelerators, the improved signal integrity and thermal management offered by this technology could allow for more efficient data flow between processor and memory, reducing latency and boosting computational efficiency. The physical layer robustness translates to fewer hardware-related errors, simplifying software debugging and improving system stability. This innovation acts as an enabler for pushing the boundaries of what is possible at the software and application layers by providing a more capable underlying hardware foundation.","business_analysis":"The Package Substrate patent (US-9852977) represents a pivotal advancement in electronic packaging, poised to unlock substantial market opportunities and provide significant competitive advantages for businesses in the semiconductor and electronics industries. As the demand for smaller, faster, and more reliable electronic devices continues its exponential growth, the fundamental limitations of traditional package substrates have become increasingly apparent. This innovation directly addresses these critical pain points, offering a compelling value proposition across various market segments.\n\n**Market Opportunity Size and Growth:**\nThe global semiconductor packaging market is a multi-billion dollar industry, projected to grow significantly in the coming years, driven by emerging technologies such as Artificial Intelligence, 5G/6G, IoT, autonomous vehicles, and high-performance computing. Within this, advanced packaging solutions are a key growth driver. The Package Substrate's ability to enhance signal integrity, thermal management, and mechanical reliability makes it highly relevant for these high-growth sectors. Its application could span from premium consumer electronics (smartphones, wearables) to mission-critical industrial and automotive systems, expanding the total addressable market for advanced substrates.\n\n**Competitive Advantages:**\nCompanies that adopt or license the Package Substrate technology will gain a significant competitive edge. This invention allows for: \n1.  **Superior Performance:** Enabling higher operating frequencies and faster data transfer rates, leading to more powerful and responsive end products.\n2.  **Enhanced Reliability:** Reducing failure rates due to thermal stress and mechanical shock, translating to lower warranty costs and improved brand reputation.\n3.  **Increased Miniaturization:** Facilitating higher integration densities, allowing for more compact and aesthetically appealing designs, which is a key differentiator in consumer markets.\n4.  **Cost Efficiency (Long-term):** While initial adoption may involve investment, the improved yields, reduced field failures, and extended product lifecycles can lead to substantial long-term cost savings and improved profitability.\n\n**Revenue Potential and Business Models:**\nRevenue generation from the Package Substrate could manifest in several ways. For substrate manufacturers, it offers a premium product line with higher margins due to its advanced capabilities. For integrated device manufacturers (IDMs) and fabless companies, it enables the creation of differentiated, high-performance products that command higher prices and capture greater market share. Licensing opportunities also exist for the patent holder, allowing for royalty revenues from its widespread adoption. Furthermore, the technology could foster new business models centered around specialized packaging services for complex chip designs.\n\n**Strategic Positioning:**\nStrategically, this innovation positions adopters at the forefront of advanced packaging technology. It provides a foundational technology that can support future generations of chip design, allowing companies to future-proof their product roadmaps. By overcoming technical barriers that current solutions face, the Package Substrate enables companies to enter or expand into demanding markets where reliability and performance are paramount. This could lead to strategic partnerships and collaborations with leading semiconductor firms and system integrators.\n\n**ROI Projections:**\nThe return on investment for companies leveraging the Package Substrate is expected to be substantial. Reduced product recalls, lower customer support costs, and increased customer satisfaction due to enhanced product reliability will directly impact the bottom line. Furthermore, the ability to develop cutting-edge products faster and gain market leadership in high-growth segments will drive significant revenue growth and shareholder value. The long-term competitive advantage derived from superior product performance and reliability will likely yield a strong, sustained ROI, solidifying a company's position in the fiercely competitive electronics market.","faqs":[{"answer":"The Package Substrate patent (US-9852977) introduces a novel and advanced type of electronic package substrate. It's the foundational component upon which integrated circuits, or 'chips,' are mounted and connected to the rest of an electronic device. Unlike traditional, purely rigid substrates, this invention features a multi-layered design that intelligently combines different material properties.\n\nSpecifically, the Package Substrate includes a rigid dielectric material layer, which provides structural stability, and a first wiring layer with metal wires formed on this rigid layer for electrical conductivity. The key innovation is the inclusion of a first flexible dielectric material layer formed directly on the first wiring layer. This hybrid structure aims to significantly enhance the performance, reliability, and integration capabilities of electronic packages by leveraging the strengths of both rigid and flexible materials.\n\nThis technology is designed to address critical challenges in modern electronics, such as maintaining signal integrity at high frequencies, managing thermal stresses, and enabling higher component densities in smaller form factors. By doing so, the Package Substrate paves the way for the next generation of high-performance and highly durable electronic devices across various industries.","question":"What is Package Substrate?"},{"answer":"The Package Substrate works by integrating a unique combination of materials in a layered architecture to optimize both electrical performance and mechanical robustness. At its base, a rigid dielectric material layer provides a sturdy, stable platform, essential for precise component placement and overall structural integrity. This rigid layer is similar to the conventional foundation of many circuit boards.\n\nOn top of this rigid base, a first wiring layer is meticulously fabricated. This layer consists of fine metal wires, typically copper, which are patterned to create the intricate electrical pathways for data signals, power, and ground connections. The design of these wires is crucial for ensuring efficient and high-speed signal transmission.\n\nThe innovative aspect of the Package Substrate is the formation of a first flexible dielectric material layer directly over this wiring layer. This flexible layer serves multiple critical functions. Electrically, it can contribute to improved signal integrity by providing a superior dielectric environment, reducing signal loss and interference at high frequencies. Mechanically, its inherent flexibility acts as a stress absorber, mitigating the damaging effects of thermal expansion and contraction mismatches between the silicon chip and the rigid substrate. This flexibility prevents microscopic cracks and delamination, significantly enhancing the device's long-term reliability and operational lifespan. In essence, it provides a stable electrical environment while offering mechanical compliance.","question":"How does Package Substrate work?"},{"answer":"The Package Substrate patent (US-9852977) primarily solves the multifaceted challenges arising from the relentless demand for smaller, faster, and more reliable electronic devices. As integrated circuits (chips) become increasingly powerful and compact, traditional, purely rigid package substrates encounter several critical limitations.\n\nFirstly, these rigid substrates struggle with **signal integrity** at high operating frequencies. Signals can degrade, suffer from crosstalk, or experience impedance mismatches, leading to slower performance and data errors. Secondly, **thermal management and mechanical reliability** are major issues. The constant heating and cooling cycles of high-power chips cause materials to expand and contract differently. Rigid substrates cannot flex, leading to significant mechanical stress, solder joint fatigue, and eventual package failure, thereby reducing device lifespan. Thirdly, achieving **high integration density** and miniaturization becomes incredibly difficult and costly on rigid platforms, limiting how many connections and components can be packed into a small space.\n\nThe Package Substrate addresses these by providing a hybrid solution that maintains signal clarity, absorbs thermal stresses, and facilitates ultra-fine interconnects, thereby overcoming the performance, reliability, and miniaturization bottlenecks of prior art.","question":"What problem does Package Substrate solve?"},{"answer":"The patent for Package Substrate (US-9852977) does not list inventors or an assignee in the provided data. Typically, patent documents meticulously credit the individual inventors who contributed to the conception of the invention and the entity (assignee) to whom the patent rights are transferred or assigned, usually a company or research institution.\n\nWithout this information, it is not possible to identify the specific individuals or organization responsible for developing this innovative Package Substrate technology. This detail is crucial for understanding the intellectual lineage and potential commercialization path of the invention.\n\nIn a complete patent record, the 'Inventors' section would list the names of the individuals, and the 'Assignee' section would name the company or organization that owns the patent. For the Package Substrate, this information would provide valuable context about its origin and the entities driving its development.","question":"Who invented Package Substrate?"},{"answer":"The Package Substrate patent (US-9852977) offers several key benefits that address critical needs in modern electronics manufacturing and design.\n\nFirstly, it provides **superior signal integrity**. By intelligently combining rigid and flexible dielectric materials, this technology minimizes signal loss, crosstalk, and impedance mismatches, ensuring cleaner and faster data transmission. This is crucial for high-speed applications like AI processors, 5G/6G communication, and high-performance computing.\n\nSecondly, the Package Substrate delivers **enhanced mechanical robustness and reliability**. The flexible dielectric layer acts as a compliant buffer, effectively absorbing and distributing the stresses caused by thermal expansion differences between the chip and the substrate. This significantly reduces the risk of delamination, cracking, and solder joint fatigue, leading to a much longer operational lifespan for electronic devices.\n\nThirdly, it enables **higher integration density and miniaturization**. The design allows for finer pitch wiring and more complex routing patterns within a compact footprint. This facilitates packing more functionality into smaller devices, which is essential for consumer electronics, wearables, and advanced IoT applications. These benefits collectively position the Package Substrate as a foundational technology for next-generation electronics.","question":"What are the key benefits of Package Substrate?"},{"answer":"The Package Substrate patent (US-9852977) differentiates itself from prior art by offering a unique hybrid material architecture that overcomes the inherent limitations of conventional substrates. Prior art typically involves either purely rigid substrates (like FR-4 or BT resin) or purely flexible substrates (like polyimide flex circuits), each with distinct trade-offs.\n\nRigid substrates offer structural stability but are prone to thermal-mechanical stress failures due to CTE mismatches and struggle with signal integrity at very high frequencies. Purely flexible substrates provide compliance but often lack the rigidity for robust component attachment and efficient thermal management. The Package Substrate, in contrast, combines a rigid dielectric material layer for structural integrity with a flexible dielectric material layer formed over the wiring. This strategic integration leverages the best of both worlds.\n\nThis hybrid design provides superior stress relief, improved signal integrity through optimized dielectric properties, and enables higher density interconnects than either purely rigid or purely flexible solutions alone. It effectively mitigates the weaknesses of existing technologies, offering a more robust, higher-performing, and reliable foundation for advanced electronic components. This innovative approach represents a significant departure from traditional packaging methodologies.","question":"How is Package Substrate different from prior art?"},{"answer":"The Package Substrate patent (US-9852977) is poised to have a transformative impact across a wide range of industries that rely heavily on high-performance, reliable, and compact electronics.\n\n**High-Performance Computing (HPC) and Artificial Intelligence (AI):** The enhanced signal integrity and thermal management capabilities are crucial for advanced processors, GPUs, and AI accelerators, enabling faster data processing and more efficient computing.\n\n**Telecommunications (5G/6G):** The ability to handle ultra-high frequencies with minimal signal loss makes the Package Substrate ideal for next-generation mobile communication devices, base stations, and network infrastructure.\n\n**Automotive and Aerospace:** The improved mechanical robustness and reliability under extreme temperature fluctuations and vibrations are vital for mission-critical electronic systems in vehicles, aircraft, and spacecraft, where safety and longevity are paramount.\n\n**Consumer Electronics:** From smartphones and tablets to wearables and smart home devices, the Package Substrate will enable thinner, lighter, more durable, and more powerful gadgets with extended battery life and enhanced functionality.\n\n**Industrial IoT and Medical Devices:** For industrial sensors, robotics, and implantable medical devices, the combination of miniaturization, high reliability, and robust performance offered by this technology is invaluable. The Package Substrate is truly a cross-industry enabler for future technological advancements.","question":"What industries will Package Substrate impact?"},{"answer":"The Package Substrate patent, identified as US-9852977, was officially filed on **2016-11-15**. This date marks when the patent application was submitted to the patent office, initiating the examination process.\n\nSubsequently, the patent was published on **2017-12-26**. The publication date typically signifies when the patent application (or the granted patent) is made publicly available, allowing the public to review the details of the invention. While the term 'granted' is not explicitly provided in the data, the 'Publication Date' of 2017-12-26 for a patent number in the US-9 million range usually indicates the date it was issued as a granted patent.\n\nTherefore, the invention described in the Package Substrate patent has been part of the public domain and intellectual property landscape since its publication in late 2017, following its filing in late 2016. This timeline is typical for the patent examination and granting process, reflecting the period during which the technology was assessed for novelty, non-obviousness, and utility.","question":"When was Package Substrate filed/granted?"},{"answer":"The commercial applications of the Package Substrate patent (US-9852977) are extensive and diverse, spanning nearly every sector that utilizes advanced electronics. Its core benefits—enhanced performance, superior reliability, and improved miniaturization—make it highly desirable for a wide array of products.\n\nIn **consumer electronics**, this technology can lead to thinner, lighter, and more powerful smartphones, tablets, and wearables with extended durability and battery life. For **high-performance computing and data centers**, it enables faster processors, memory modules, and network interfaces, crucial for AI training, big data analytics, and cloud infrastructure. In the **automotive industry**, the Package Substrate's robustness under thermal stress makes it ideal for advanced driver-assistance systems (ADAS), infotainment systems, and engine control units, enhancing safety and longevity.\n\n**Aerospace and defense** applications will benefit from its reliability in extreme conditions, while **medical devices** can leverage its miniaturization and consistent performance for implantable devices and portable diagnostic equipment. Furthermore, in **industrial IoT**, this technology can power more resilient and efficient sensors and control systems operating in harsh environments. The Package Substrate is a foundational enabler, driving innovation and competitive advantage across these high-growth markets.","question":"What are the commercial applications of Package Substrate?"},{"answer":"The Package Substrate patent (US-9852977) lays a robust foundation for numerous future developments in electronic packaging. One key area of expected advancement is its deeper integration into **heterogeneous integration and chiplet architectures**. As the industry moves away from monolithic chips, this technology's ability to provide a reliable, high-performance interface for diverse chiplets from different manufacturers will be crucial.\n\nFurther developments may focus on **enhanced thermal management solutions** integrated directly within or alongside the flexible and rigid layers. This could involve microfluidic cooling channels or advanced heat spreading materials to cope with ever-increasing power densities. We can also anticipate the exploration of **even more advanced flexible dielectric materials** with ultra-low dielectric constants and dissipation factors, pushing signal integrity to unprecedented levels for future terahertz-frequency applications.\n\nMoreover, the principles of the Package Substrate could evolve to support **more complex 3D packaging strategies**, allowing for robust vertical stacking of multiple ICs while mitigating the associated thermal and mechanical challenges. This innovation also has potential in **flexible hybrid electronics (FHE)**, bridging the gap between rigid PCBs and fully flexible systems to enable novel form factors for wearables, smart textiles, and conformable sensors. The Package Substrate is a dynamic platform, ripe for continuous refinement and expansion into new technological frontiers.","question":"What are the future developments expected for Package Substrate?"}],"topics":["Package Substrate","electronic packaging","semiconductor patent","rigid dielectric","flexible dielectric","miniaturization","performance","scaling"],"tech_cluster":null},"seo":{"title":"Package Substrate - Advanced Electronic Packaging Patent US-9852977","description":"Discover the 'Package Substrate' patent US-9852977, a groundbreaking innovation combining rigid and flexible dielectric layers for superior performance and reliability in electronics.","keywords":["Package Substrate","electronic packaging","semiconductor patent","rigid dielectric","flexible dielectric","high-density interconnect","signal integrity","thermal management","US-9852977","advanced packaging","microelectronics","patent analysis"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852977","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852977","citation_suggestion":"Patentable. \"Package substrate\" (US-9852977). https://patentable.app/patents/US-9852977","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852977","json":"https://patentable.app/api/llm-context/US-9852977","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:15:41.950Z"}