{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9852992","patent":{"patent_number":"US-9852992","title":"Semiconductor device and manufacturing method thereof","assignee":null,"inventors":[],"filing_date":"2017-04-11T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings."},"analysis":{"summary":"The patent titled \"Semiconductor Device and Manufacturing Method Thereof\" (US-9852992) introduces a groundbreaking manufacturing process designed to significantly enhance the performance and efficiency of semiconductor devices. The core innovation lies in its unique method for creating ultra-low-k dielectric isolation between adjacent metal wirings through the controlled formation of air gaps.\n\nThe primary problem this invention addresses is the pervasive issue of parasitic capacitance in miniaturized integrated circuits. As metal interconnects become increasingly dense and closely packed, unwanted electrical coupling between them leads to signal delays, crosstalk, and increased power consumption, hindering the overall speed and efficiency of the chip. Existing low-k dielectric materials offer some improvement but cannot match the insulating properties of air.\n\nThis patent's key technical approach involves a precise, multi-step process. First, a dielectric layer is formed over a substrate, and metal wirings are embedded within recesses in this layer. Crucially, a mask layer is then applied with an opening that is specifically designed to be *narrower* than the actual space between adjacent metal wirings. This allows for controlled etching of a narrow groove into the first dielectric layer, precisely between the metal lines. Subsequently, a second dielectric layer is formed, which effectively seals off this groove, thereby encapsulating an air gap. This trapped air, with its dielectric constant of approximately 1, acts as a superior insulator compared to conventional solid dielectrics.\n\nThe business value and applications of this technology are substantial. By dramatically reducing parasitic capacitance, the Semiconductor Device and Manufacturing Method Thereof enables the production of faster, more power-efficient, and more reliable integrated circuits. This is critical for high-growth sectors such as artificial intelligence, high-performance computing, 5G communication, and advanced mobile devices, where every nanometer and picofarad of performance gain is vital. Manufacturers adopting this method can achieve a significant competitive advantage by offering chips that push the boundaries of current performance limits.\n\nThe market opportunity for this innovation is immense, as it addresses a fundamental scaling challenge in semiconductor manufacturing. As the demand for increasingly complex and compact electronics continues unabated, technologies that can reduce power consumption and boost speed without compromising reliability will be essential. This patent provides a scalable and robust solution, positioning it to become a foundational technique in next-generation semiconductor fabrication processes.","layman_explanation":"### 1. What Problem Does This Solve?\nImagine a bustling city with hundreds of cars (electrical signals) trying to get from one point to another on narrow, parallel streets (metal wirings) without traffic lights. When these streets are too close, cars inevitably bump into each other, slow down, or even get confused about which lane they're in. In the world of microchips, this 'bumping' is called *parasitic capacitance* – an unwanted electrical interaction between adjacent wires. As chips get smaller and more powerful, these wires are packed tighter than ever, making this problem worse. It leads to slower processing speeds, higher energy consumption (draining your phone battery faster), and less reliable performance in everything from your smartphone to supercomputers. Existing solutions use special materials to reduce this 'bumping,' but they're never as good as having a completely empty space.\n\n### 2. How Does It Work?\nThe patent, titled \"Semiconductor Device and Manufacturing Method Thereof,\" introduces a remarkably clever solution: creating tiny pockets of air, or 'air gaps,' right where they're needed most – between these critical metal wires. Think of it like building invisible, perfectly insulating walls between those busy city streets. Air is the ultimate insulator because it doesn't conduct electricity well at all, meaning it stops the 'whispering' or 'bumping' between wires almost completely.\n\nThe manufacturing process involves several precise steps:\n1.  **Laying the Foundation:** First, a base insulating layer is put down on the chip's surface.\n2.  **Building the Roads:** Then, the tiny metal wires are created within channels in this insulating layer.\n3.  **The Clever Stencil:** Here's the innovative part: a special 'stencil' (a mask layer) is placed over the wires. This stencil has openings that are intentionally *narrower* than the actual space between the metal wires. This is key for precision.\n4.  **Sculpting the Gaps:** Using this stencil, a small, controlled groove is etched into the insulating layer, right between the wires. Because the stencil opening was narrower, the groove is perfectly sized.\n5.  **Sealing the Air:** Finally, another insulating layer is deposited over everything. This layer seals off the newly etched groove, trapping a tiny pocket of air inside. Voilà – an air gap is formed, acting as a perfect electrical barrier.\n\nThis approach is like having a dedicated, perfectly clear lane for each car, ensuring smooth, fast, and unhindrupted travel.\n\n### 3. Why Does This Matter?\nThis innovation matters immensely because it directly impacts the fundamental performance of all modern electronics. By virtually eliminating parasitic capacitance, the Semiconductor Device and Manufacturing Method Thereof allows for:\n*   **Faster Devices:** Electrical signals can travel with minimal interference, leading to higher clock speeds and quicker data processing for everything from AI computations to everyday app usage.\n*   **Lower Power Consumption:** Less 'bumping' means less wasted energy, extending battery life in mobile devices and reducing the massive energy footprint of data centers.\n*   **Greater Reliability:** Reduced electrical noise means cleaner signals, leading to more stable and dependable chip operation.\n\nFor businesses, this translates into a significant competitive advantage. Companies that adopt this manufacturing method can produce chips that are demonstrably superior in performance and efficiency. This can unlock new product capabilities, capture larger market shares in high-growth areas like AI and 5G, and deliver a superior user experience, ultimately leading to higher profitability and market leadership. It's a foundational technology that enhances the core building blocks of the digital economy.\n\n### 4. What's Next?\nThis technology has the potential to become a standard manufacturing technique for advanced semiconductor nodes. Its real-world applications will span across all sectors requiring high-performance, energy-efficient computing. We can expect to see chips leveraging this method in future generations of smartphones, ultra-fast data center processors, autonomous vehicle systems, and sophisticated IoT devices. The market adoption timeline will likely accelerate as foundries integrate this robust and scalable solution, ensuring that the relentless demand for faster and more powerful electronics can continue to be met. For investors, this represents a pivotal patent that could underpin the next wave of innovation in silicon.","technical_analysis":"The patent \"Semiconductor Device and Manufacturing Method Thereof\" (US-9852992) describes a sophisticated fabrication methodology aimed at mitigating parasitic capacitance in advanced integrated circuits through the creation of internal air gaps. This technical analysis delves into the architectural and implementational specifics of this innovation.\n\n**Technical Architecture and Problem Statement:**\nModern semiconductor devices face an inherent challenge: as transistors and interconnects shrink, the proximity of metal lines leads to increased parasitic capacitance. This capacitance introduces RC (resistance-capacitance) delays, crosstalk, and power dissipation, which become limiting factors for device performance, especially at high frequencies. Traditional solutions involve solid low-k dielectric materials, but their dielectric constants are still significantly higher than that of vacuum or air (k≈1.0). The Semiconductor Device and Manufacturing Method Thereof addresses this by engineering true air gaps as inter-metal dielectrics.\n\n**Implementation Details and Algorithm Specifics:**\n1.  **Substrate and First Dielectric Layer Formation:** The process begins with a standard semiconductor substrate (e.g., silicon). A first dielectric layer (e.g., silicon dioxide, low-k polymer) is deposited over this substrate using conventional techniques such as Chemical Vapor Deposition (CVD) or Spin-on Dielectric (SOD).\n2.  **Metal Wiring Formation:** First recesses are formed in the first dielectric layer, typically using photolithography and etching. These recesses are then filled with conductive material (ee.g., copper, aluminum) through processes like electroplating or physical vapor deposition (PVD), followed by chemical mechanical planarization (CMP) to create planarized metal wirings extending in a primary direction.\n3.  **Mask Layer Application:** A mask layer is then formed over the metal wirings and the remaining first dielectric layer. This mask layer is critical. It contains a 'first opening' precisely aligned above the space between two adjacent metal wirings and extending in the same direction as the wirings. The crucial parameter here is the width of this first opening in the direction perpendicular to the wirings. This width is *intentionally designed to be smaller* than the actual physical space between the adjacent metal wirings. This 'sub-gap' opening is key to controlled etching and air gap formation.\n4.  **First Groove Etching:** Using the precisely patterned mask layer as an etching mask, a first groove is formed by selectively etching the first dielectric layer located between the adjacent metal wirings. Because the mask opening is narrower than the full inter-wiring gap, the etching process creates a controlled void or trench that is narrower than the full space. This selective etching can be achieved using anisotropic dry etching techniques (e.g., Reactive Ion Etching - RIE) that provide high aspect ratio control.\n5.  **Second Dielectric Layer and Air Gap Formation:** Finally, a second dielectric layer is formed over the entire structure, including the newly etched groove and the exposed metal wirings. This layer is deposited in a manner that effectively covers and seals the first groove, encapsulating the empty space within it. This encapsulated empty space constitutes the 'first air gap'. The deposition method for the second dielectric layer is critical to ensure a void-free seal above the groove while preserving the air gap. Techniques like atomic layer deposition (ALD) or conformal CVD followed by planarization might be considered to achieve this precise encapsulation.\n\n**Integration Patterns and Performance Characteristics:**\nThe integration of this method into existing BEOL (Back-End-Of-Line) processes appears feasible, leveraging standard photolithography, etching, and deposition tools. The primary performance characteristic improved is the reduction of parasitic capacitance (C). By replacing a solid dielectric (k > 1) with an air gap (k ≈ 1), the capacitance between adjacent lines is significantly lowered. This directly translates to:\n*   **Reduced RC Delay:** Faster signal propagation, enabling higher clock frequencies and improved circuit speed.\n*   **Lower Power Consumption:** Reduced charging and discharging current for interconnects.\n*   **Minimized Crosstalk:** Better signal integrity due to weaker capacitive coupling between adjacent lines.\n*   **Enhanced Reliability:** Potentially reduced heat generation from resistive losses, contributing to device longevity.\n\n**Code-Level Implications (Analogous):**\nWhile this patent is hardware-centric, its implications for design automation and simulation are significant. EDA (Electronic Design Automation) tools would need to accurately model the presence and geometry of these air gaps to predict circuit performance. Simulation models for parasitic extraction would require updated rules to account for the ultra-low-k regions. Furthermore, physical verification tools would need to incorporate design rules for the mask opening width relative to the inter-wiring space to ensure manufacturability and correct air gap formation. This innovation pushes the boundaries of interconnect design, requiring sophisticated co-optimization between process technology and circuit design.","business_analysis":"The patent \"Semiconductor Device and Manufacturing Method Thereof\" (US-9852992) presents a compelling business opportunity within the fiercely competitive semiconductor industry. Its core innovation – the precise formation of air gaps as inter-metal dielectrics – directly addresses critical performance and power bottlenecks, positioning it for significant market disruption.\n\n**Market Opportunity Size:**\nThe global semiconductor market is a multi-trillion-dollar industry, with interconnect technology being a foundational component of every integrated circuit. As devices continue to shrink (Moore's Law scaling) and demand for higher performance and lower power surges, the 'interconnect bottleneck' becomes increasingly pronounced. The market for advanced dielectric materials and manufacturing processes to mitigate parasitic capacitance is therefore enormous and growing. This patent targets a fundamental improvement in chip architecture, applicable across virtually all segments: high-performance computing (HPC), artificial intelligence (AI) accelerators, 5G infrastructure, mobile processors, IoT devices, and automotive electronics. The total addressable market for solutions that enhance interconnect performance runs into hundreds of billions of dollars annually.\n\n**Competitive Advantages:**\n1.  **Superior Dielectric Performance:** Air (k≈1.0) offers the lowest possible dielectric constant, outperforming all solid low-k materials (k>2.0). This provides an inherent, fundamental performance advantage in reducing parasitic capacitance and RC delay.\n2.  **Process Compatibility:** The method described appears to be largely compatible with existing semiconductor fabrication processes (photolithography, etching, deposition), reducing the barriers to adoption and capital expenditure for foundries.\n3.  **Cost-Effectiveness:** Utilizing air as the primary insulating medium can potentially reduce reliance on expensive, exotic low-k dielectric materials, leading to cost efficiencies in manufacturing.\n4.  **Scalability:** The precise control over air gap formation using a specifically designed mask opening suggests a scalable solution for future technology nodes, where inter-wiring spacing will become even tighter.\n\n**Revenue Potential and Business Models:**\nThis technology could generate revenue through several models:\n*   **Licensing:** Semiconductor foundries (e.g., TSMC, Samsung Foundry, Intel Foundry Services) would be prime licensees, paying royalties for the right to implement this manufacturing method in their advanced nodes.\n*   **Joint Ventures/Partnerships:** Collaboration with leading IDMs (Integrated Device Manufacturers) or fabless companies to integrate this technology into their next-generation chip designs.\n*   **Specialized IP Provider:** A company holding this patent could position itself as a key IP provider for ultra-low-k interconnect solutions.\n\nThe revenue potential is significant, given the widespread applicability and the critical nature of the problem it solves. Even a small percentage of the global chip market adopting this technology could translate into substantial licensing fees.\n\n**Strategic Positioning:**\nCompanies leveraging the \"Semiconductor Device and Manufacturing Method Thereof\" can strategically position themselves as leaders in high-performance, low-power chip manufacturing. This innovation offers a pathway to differentiate products by delivering superior speed, energy efficiency, and reliability. It enables the development of next-generation processors that can meet the escalating demands of data-intensive applications like AI and machine learning, where interconnect performance is paramount.\n\n**ROI Projections:**\nInvesting in the implementation or licensing of this technology offers a strong return on investment. For foundries, it means attracting more customers seeking cutting-edge performance. For IDMs, it translates to competitive products with better power-performance-area (PPA) metrics, leading to higher market share and profitability. The reduction in power consumption alone can offer significant operational cost savings for large-scale data centers utilizing chips manufactured with this method. The long-term ROI is tied to sustaining Moore's Law and enabling continued innovation in advanced electronics, securing future market relevance and profitability.","faqs":[{"answer":"The \"Semiconductor Device and Manufacturing Method Thereof\" is a patent (US-9852992) that describes an innovative process for manufacturing semiconductor devices with enhanced electrical performance. At its core, this patent introduces a novel technique for creating precisely controlled air gaps between adjacent metal wirings within a microchip.\n\nThese air gaps act as ultra-low-k dielectric insulators, meaning they are extremely effective at preventing unwanted electrical interference, known as parasitic capacitance. By leveraging air, which has a dielectric constant of approximately 1.0 (the lowest possible), the invention significantly improves signal integrity and reduces energy loss compared to traditional solid insulating materials.\n\nThe overall goal of the Semiconductor Device and Manufacturing Method Thereof is to enable the production of faster, more power-efficient, and more reliable integrated circuits, addressing a critical bottleneck in modern chip design as components continue to miniaturize.","question":"What is Semiconductor Device and Manufacturing Method Thereof?"},{"answer":"The Semiconductor Device and Manufacturing Method Thereof works through a multi-step manufacturing process designed for precision air gap formation. First, a base dielectric layer is formed over a substrate, and metal wirings are created within recesses in this layer.\n\nThe ingenious step involves applying a mask layer with a critical feature: its opening is *narrower* than the actual space between adjacent metal wirings. This precisely sized mask is then used to selectively etch a groove into the first dielectric layer, specifically between the metal wirings. Because the mask opening is narrower, the etching process is highly controlled, creating a well-defined void.\n\nFinally, a second dielectric layer is formed over the entire structure, which seals off the newly etched groove, effectively trapping air within it. This encapsulated air pocket then serves as an ultra-low-k dielectric, dramatically reducing parasitic capacitance between the adjacent metal lines. This method ensures robust and reliable air gap integration.","question":"How does Semiconductor Device and Manufacturing Method Thereof work?"},{"answer":"The Semiconductor Device and Manufacturing Method Thereof primarily solves the problem of parasitic capacitance in advanced semiconductor devices. As microchips become increasingly dense, the metal wires (interconnects) that carry electrical signals are packed very closely together. This proximity leads to unwanted electrical coupling between adjacent wires, known as parasitic capacitance.\n\nThis parasitic capacitance causes several critical issues: it slows down signal propagation (RC delay), increases power consumption (as more energy is needed to charge and discharge these unwanted capacitors), and degrades signal integrity through crosstalk. These problems become major bottlenecks for achieving higher clock speeds, lower power consumption, and greater reliability in modern integrated circuits.\n\nBy introducing air gaps, the Semiconductor Device and Manufacturing Method Thereof provides a superior insulating medium, effectively minimizing these detrimental electrical interactions and enabling chips to perform faster and more efficiently.","question":"What problem does Semiconductor Device and Manufacturing Method Thereof solve?"},{"answer":"The patent \"Semiconductor Device and Manufacturing Method Thereof\" (US-9852992) was filed by its inventors. The specific names of the inventors are typically listed on the patent document itself, though not provided in the prompt data. Similarly, the assignee, which is the entity or company to whom the patent rights are transferred, is also not provided in the prompt data.\n\nHowever, the innovation itself, the Semiconductor Device and Manufacturing Method Thereof, represents a collective effort in the field of semiconductor research and development to address fundamental challenges in microchip manufacturing. Such patents are often the result of extensive R&D within major semiconductor companies or research institutions aimed at pushing the boundaries of technology.","question":"Who invented Semiconductor Device and Manufacturing Method Thereof?"},{"answer":"The Semiconductor Device and Manufacturing Method Thereof offers several significant benefits for semiconductor devices and the broader electronics industry.\n\nFirstly, it leads to **significantly faster chips**. By dramatically reducing parasitic capacitance, electrical signals can travel through the interconnects with much less delay, enabling higher operating frequencies and overall faster processing speeds. Secondly, it results in **lower power consumption**. Less electrical interference means less energy is wasted, which translates to longer battery life for mobile devices and reduced energy costs for data centers.\n\nThirdly, the innovation enhances **signal integrity and reliability**. Reduced crosstalk and noise lead to cleaner, more stable signals, improving the overall dependability of the integrated circuit. Finally, the Semiconductor Device and Manufacturing Method Thereof provides a **scalable solution** for future technology nodes, allowing for continued miniaturization and performance scaling as chip designs become even more complex and compact.","question":"What are the key benefits of Semiconductor Device and Manufacturing Method Thereof?"},{"answer":"The Semiconductor Device and Manufacturing Method Thereof differs significantly from prior art in its approach to inter-metal dielectric insulation. Previous generations of technology primarily focused on developing solid low-k dielectric materials, such as porous silicon dioxide or organic polymers.\n\nWhile these materials offered improvements over traditional silicon dioxide, their dielectric constants were still significantly greater than 1.0. The Semiconductor Device and Manufacturing Method Thereof, however, directly integrates *air* (k≈1.0) as the insulating medium. This provides a fundamental advantage, as air is the ultimate low-k dielectric.\n\nCrucially, this patent outlines a precise and controlled manufacturing method for forming these air gaps, utilizing a mask with an opening *narrower* than the inter-wiring space, and robust encapsulation. This addresses the reliability and manufacturability challenges that hindered earlier attempts at air gap technology, making it a more robust and scalable solution compared to porous materials or less controlled void formation techniques of prior art.","question":"How is Semiconductor Device and Manufacturing Method Thereof different from prior art?"},{"answer":"The Semiconductor Device and Manufacturing Method Thereof is poised to impact a wide array of industries that rely on high-performance, energy-efficient semiconductor devices.\n\n**High-Performance Computing (HPC) and Artificial Intelligence (AI):** Faster and more efficient processors are critical for training complex AI models, large-scale data analytics, and scientific simulations. This technology enables the development of next-generation CPUs, GPUs, and AI accelerators.\n\n**Mobile and Consumer Electronics:** Longer battery life, faster app performance, and cooler operating temperatures are key for smartphones, tablets, wearables, and IoT devices. The Semiconductor Device and Manufacturing Method Thereof directly contributes to these improvements.\n\n**Telecommunications:** With the rise of 5G and future wireless standards, high-speed, low-latency communication chips are essential. This innovation can enhance the performance of network infrastructure and communication devices. Additionally, it will benefit **Automotive Electronics** for advanced driver-assistance systems (ADAS) and autonomous vehicles, and **Cloud Computing** infrastructure by reducing the power consumption and enhancing the speed of data center processors.","question":"What industries will Semiconductor Device and Manufacturing Method Thereof impact?"},{"answer":"The patent for \"Semiconductor Device and Manufacturing Method Thereof\" (US-9852992) was filed on **April 11, 2017**. Following the examination process, it was subsequently published on **December 26, 2017**.\n\nThe filing date marks when the inventors submitted their application to the patent office, establishing their priority date for the invention. The publication date signifies when the patent document was made publicly available, allowing the broader technical and business communities to review the details of the Semiconductor Device and Manufacturing Method Thereof. This timeline indicates a relatively swift examination and publication process, highlighting the potential relevance and novelty of the innovation at the time of its filing.","question":"When was Semiconductor Device and Manufacturing Method Thereof filed/granted?"},{"answer":"The commercial applications of the Semiconductor Device and Manufacturing Method Thereof are extensive, spanning across virtually all segments of the electronics industry where high-performance and energy efficiency are critical. Its core benefit of reducing parasitic capacitance translates directly into tangible product advantages.\n\nKey applications include **advanced microprocessors** for personal computers, servers, and data centers, enabling faster processing speeds and lower operational costs. In **mobile devices** like smartphones and tablets, it leads to longer battery life and improved responsiveness. For **AI and machine learning accelerators**, the enhanced signal integrity and speed are crucial for complex computations. Furthermore, it will benefit **5G and future communication chips**, **high-performance memory devices**, and **specialized integrated circuits** for automotive, aerospace, and industrial applications.\n\nManufacturers adopting the Semiconductor Device and Manufacturing Method Thereof can gain a significant competitive edge by offering products with superior power-performance-area (PPA) metrics, leading to increased market share and profitability across these high-growth sectors.","question":"What are the commercial applications of Semiconductor Device and Manufacturing Method Thereof?"},{"answer":"Future developments for the Semiconductor Device and Manufacturing Method Thereof are likely to focus on further optimizing its integration and extending its applicability to even more advanced technologies. We can expect research into refining the manufacturing process for even tighter interconnect pitches, pushing the limits of miniaturization while maintaining air gap integrity.\n\nFurther advancements might include exploring its integration with **3D stacking technologies** (e.g., 3D-ICs, chiplets) to enhance vertical communication between stacked dies, or adapting the principles for **novel materials** and device architectures. Reliability studies will continue to be crucial to ensure the long-term stability and performance of air-gap-insulated structures under various operational stresses.\n\nUltimately, the Semiconductor Device and Manufacturing Method Thereof is expected to evolve as a foundational technology, enabling the continued scaling of semiconductor devices and paving the way for innovations in quantum computing, advanced sensing, and other emerging fields that demand ultra-high performance and efficiency. Its robust approach to leveraging air as an insulator positions it for sustained relevance in the future of microelectronics.","question":"What are the future developments expected for Semiconductor Device and Manufacturing Method Thereof?"}],"topics":["semiconductor device","manufacturing method","air gap technology","low-k dielectric","parasitic capacitance","relentless","scaling","semiconductor"],"tech_cluster":null},"seo":{"title":"Semiconductor Device and Manufacturing Method Thereof - Patent US-9852992","description":"Discover the groundbreaking Semiconductor Device and Manufacturing Method Thereof patent. Learn how air gaps revolutionize chip performance, reduce power, and enhance reliability.","keywords":["semiconductor device","manufacturing method","air gap technology","low-k dielectric","parasitic capacitance","chip performance","microelectronics","H01L","patent US-9852992","interconnects","chip fabrication","advanced packaging","power efficiency","signal integrity"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9852992","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9852992","citation_suggestion":"Patentable. \"Semiconductor device and manufacturing method thereof\" (US-9852992). https://patentable.app/patents/US-9852992","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9852992","json":"https://patentable.app/api/llm-context/US-9852992","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T03:49:45.789Z"}