{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9853012","patent":{"patent_number":"US-9853012","title":"Semiconductor packages having through electrodes and methods of fabricating the same","assignee":null,"inventors":[],"filing_date":"2016-01-29T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":9,"abstract":"Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively."},"analysis":{"summary":"The patent \"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same\" (US-9853012) introduces a sophisticated and highly efficient method for constructing advanced semiconductor packages with vertical integration. At its core, this innovation addresses the critical need for increased chip density and improved electrical performance in modern electronic devices, particularly in the context of miniaturization and high-speed data processing.\n\nThe core innovation lies in its hybrid approach to chip stacking. The method involves forming a wafer-level package where first semiconductor chips are stacked on a second chip. Simultaneously, chip-level packages are created by stacking fourth semiconductor chips on a third chip. These modular chip-level packages are then precisely stacked onto the back surface of the second semiconductor substrate of the wafer-level package, creating a multi-tier, highly integrated assembly.\n\nA key technical approach described is the meticulous process of polishing the first mold layer and the first semiconductor chips. This critical step exposes pre-formed 'first through electrodes' embedded within the first semiconductor chip. These exposed electrodes are then directly connected to 'outer electrodes', establishing robust and efficient vertical electrical pathways through the entire stacked package. This direct connection minimizes signal loss, reduces latency, and significantly enhances the overall electrical performance of the device.\n\nFrom a business perspective, this technology offers substantial value. It provides a scalable and potentially more cost-effective manufacturing solution for high-density semiconductor packages compared to some prior art methods like complex Through-Silicon Via (TSV) processes. The improved integration density and electrical characteristics make it ideal for next-generation consumer electronics, artificial intelligence hardware, IoT devices, and high-performance computing. The market opportunity is vast, driven by the continuous demand for smaller, faster, and more energy-efficient electronic components across virtually every industry. This patent positions its implementers at the forefront of advanced packaging technology, offering a competitive edge in a rapidly evolving market.","layman_explanation":"### What Problem Does This Solve?\nImagine trying to build a taller, more powerful computer without making it bigger. For decades, engineers made chips smaller and smaller, but that's getting really hard. The next big frontier is stacking chips on top of each other, like building a multi-story building of computer brains. However, connecting all those 'floors' efficiently is a huge challenge. Older methods were like building long, winding staircases between floors – slow, bulky, and prone to breaking. This made devices thicker, less powerful, or too expensive to produce. The core business problem is the increasing demand for miniaturized, high-performance electronics that current packaging techniques struggle to deliver cost-effectively and reliably.\n\n### How Does It Work?\n\"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same\" solves this by introducing a brilliant new architectural approach to chip stacking. Think of it like a LEGO system for microchips. Instead of just stacking flat pieces, this invention allows for the creation of intricate, multi-level chip structures. It starts by making some 'base' chip packages (wafer-level packages) and then smaller, modular 'mini-packages' (chip-level packages). The clever part is then stacking these mini-packages onto the base package. The real innovation lies in creating tiny, direct 'through electrodes' – essentially, super-fast, vertical elevators for electricity – that go straight through the chip layers. After stacking, a precise 'polishing' step reveals these hidden elevators, allowing external connections to be formed directly onto them. This eliminates the need for long, inefficient wires and ensures that all parts of the stacked chip tower can communicate instantly.\n\n### Why Does This Matter?\nThis innovation matters immensely because it directly impacts the performance, size, and cost of almost every electronic device we use. For businesses, this means:\n*   **Miniaturization & Performance:** Products can be significantly smaller, lighter, and more powerful. This is crucial for smartphones, wearables, medical implants, and compact IoT devices, allowing companies to create highly differentiated products.\n*   **Competitive Edge in AI & HPC:** For industries relying on Artificial Intelligence or High-Performance Computing (like data centers, autonomous vehicles, or advanced analytics), this technology enables the creation of faster, more energy-efficient processors by allowing more computational power to be packed into a smaller space. This can lead to breakthroughs in AI model training and inference speeds.\n*   **Cost-Effectiveness & Scalability:** By streamlining the manufacturing process for high-density packages, this patent can lead to lower production costs and higher yields. This makes advanced packaging more accessible for a wider range of products, enhancing profitability and market reach.\n*   **Future-Proofing:** Companies adopting this technology will be at the forefront of semiconductor innovation, ready to meet the demands of future technological advancements that require extreme integration.\n\n### What's Next?\nThis technology is poised to accelerate the development of next-generation electronics across numerous sectors. We can expect to see its principles applied in the creation of ultra-compact mobile processors, high-bandwidth memory modules for AI, and integrated sensor platforms for smart cities and automotive applications. Market adoption will likely begin in high-value, performance-critical areas and then trickle down to broader consumer markets as manufacturing scales. For investors, this represents a significant opportunity in the advanced materials and semiconductor manufacturing space, promising substantial ROI for companies that successfully implement and leverage this groundbreaking packaging solution.","technical_analysis":"The patent \"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same\" (US-9853012) details a novel and robust methodology for fabricating highly integrated semiconductor packages utilizing through electrodes. This innovation directly addresses the persistent challenges of increasing package density, enhancing electrical performance, and improving manufacturing efficiency in the realm of 3D integration.\n\n**Technical Architecture and Core Innovation:**\nThe fundamental architecture described is a multi-tier stacked package built upon a hybrid approach combining wafer-level packaging (WLP) and chip-level packaging (CLP). The core innovation lies in the precise control over forming and exposing through electrodes to create efficient vertical interconnects. The system begins with a base WLP, comprising 'first semiconductor chips' stacked on a 'second semiconductor chip', encapsulated by a 'first mold layer'. Concurrently, modular CLPs are formed, each consisting of 'fourth semiconductor chips' stacked on a 'third semiconductor chip'. These CLPs are then vertically integrated onto the back surface of the 'second semiconductor substrate' of the WLP, forming a complex yet compact stacked structure.\n\n**Implementation Details and Key Steps:**\n1.  **WLP Formation:** A 'second semiconductor chip' (e.g., a base logic die or interposer) serves as the foundation. 'First semiconductor chips' (e.g., memory dies, sensor dies) are then stacked upon it. This assembly is encapsulated by a 'first mold layer', typically an epoxy molding compound (EMC) or a similar dielectric polymer, which provides mechanical support and electrical isolation.\n2.  **CLP Formation:** Separately, 'third semiconductor chips' act as base layers for 'fourth semiconductor chips'. This sub-assembly is also molded, creating self-contained, pre-tested chip-level stacks. This modularity is crucial, potentially allowing for known-good-stack (KGS) integration, improving overall yield.\n3.  **Multi-Stack Integration:** A plurality of these CLPs are then precisely aligned and stacked onto the exposed back surface of the 'second semiconductor substrate' of the WLP. This step requires advanced bonding techniques such as thermal compression bonding (TCB), solder-based bonding, or adhesive bonding, ensuring mechanical stability and electrical contact where necessary.\n4.  **Through Electrode Exposure (Critical Step):** After the multi-tier stacking and possibly further molding, the 'first mold layer' of the WLP and the 'first semiconductor chips' themselves undergo a meticulous polishing process. This is typically achieved using Chemical Mechanical Planarization (CMP) or similar precision grinding/polishing techniques. The objective is to selectively remove material until the 'first through electrodes' – pre-fabricated vertical conductive elements within the first semiconductor chips – are exposed at the surface. The precision of this step is critical; over-polishing could damage the electrodes, while under-polishing would prevent proper connection.\n5.  **Outer Electrode Formation:** Once the 'first through electrodes' are exposed, 'outer electrodes' are formed on the polished surface of the 'first semiconductor chips'. These outer electrodes are designed to directly contact and provide an external interface to the exposed through electrodes. This can involve deposition of metal layers (e.g., Cu, Al, Au) via sputtering or electroplating, followed by photolithography and etching to pattern the desired electrode geometry. These outer electrodes serve as the final connection points for external circuitry or subsequent package layers.\n\n**Algorithm Specifics and Integration Patterns:**\nWhile not an 'algorithm' in the software sense, the sequence of fabrication steps outlined constitutes a precise manufacturing algorithm. The 'stacking' and 'polishing' steps are critical. The alignment algorithms for stacking multiple CLPs onto the WLP must be highly accurate (e.g., sub-micron precision) to ensure proper electrical contact and mechanical stability. The CMP process for electrode exposure requires precise control over removal rate, slurry composition, and polishing pressure, often guided by optical or electrical endpoint detection systems to ensure uniform exposure without damage. Integration patterns involve direct electrical paths from the chip surface, through the chip body via through electrodes, to the outer electrodes, enabling high-bandwidth vertical communication.\n\n**Performance Characteristics and Code-Level Implications:**\nThe direct, short vertical interconnects created by this method significantly reduce parasitic capacitance and inductance compared to wire bonds or even some TSV implementations. This translates to:\n*   **Higher Bandwidth and Speed:** Faster data transfer rates between stacked chips.\n*   **Lower Power Consumption:** Reduced resistive and capacitive losses during signal propagation.\n*   **Improved Signal Integrity:** Less noise and cross-talk due to shorter and more direct paths.\n\nFrom a 'code-level' implication perspective (referring to hardware design/firmware), designers of chips intended for this packaging method would need to optimize I/O pad placement to align with the through electrode grid. EDA tools would require updated libraries and design rules to account for the unique 3D stack-up, thermal profiles, and electrical models specific to this packaging technology. Firmware for devices utilizing these packages might see performance gains that allow for more complex algorithms or faster execution of existing ones, particularly in memory-intensive or parallel processing applications.","business_analysis":"The patent \"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same\" (US-9853012) introduces a pivotal advancement in semiconductor packaging that carries substantial business implications across multiple high-growth sectors. This innovation directly addresses the escalating demand for smaller, more powerful, and energy-efficient electronic devices, unlocking significant market opportunities and offering a potent competitive advantage.\n\n**Market Opportunity Size:**\nThe global semiconductor packaging market is projected to reach hundreds of billions of dollars within the next decade, driven by the proliferation of 5G, AI, IoT, automotive electronics, and high-performance computing (HPC). Advanced packaging, specifically 3D integration, is a key growth driver within this market. This patent's methodology for creating high-density, high-performance stacked packages positions it to capture a substantial share of this expanding segment. Applications span consumer electronics (smartphones, wearables), enterprise (data centers, AI accelerators), industrial (IoT, automation), and specialized markets (medical, aerospace). The ability to integrate more functionality into a smaller footprint with improved electrical characteristics is a universal need, ensuring a broad and deep market penetration potential.\n\n**Competitive Advantages:**\n1.  **Superior Integration Density:** The hybrid wafer-level and chip-level stacking, combined with precise through-electrode exposure, enables unprecedented component density within a single package. This offers a distinct advantage over conventional 2D packaging and even many existing 3D techniques, leading to smaller, lighter, and more capable end products.\n2.  **Enhanced Performance:** Direct vertical interconnects via through electrodes significantly reduce signal path lengths, minimizing parasitic effects. This translates to higher operating speeds, lower power consumption, and improved signal integrity, providing a crucial performance edge in competitive markets where every nanosecond and milliwatt counts.\n3.  **Manufacturing Efficiency and Scalability:** The modular nature of chip-level packages and the detailed fabrication method outlined in the patent suggest a more streamlined and potentially higher-yield manufacturing process compared to the notoriously complex and costly Through-Silicon Via (TSV) processes. This can lead to lower unit costs and faster time-to-market.\n4.  **Flexibility for Heterogeneous Integration:** The ability to stack different types of chips (e.g., logic, memory, sensors) from various manufacturers into a single package allows for highly optimized, application-specific solutions. This flexibility is critical in an era of 'chiplet' architectures and heterogeneous computing.\n\n**Revenue Potential and Business Models:**\nCompanies that license or implement this technology could generate revenue through:\n*   **Direct Manufacturing:** Producing advanced semiconductor packages for fabless companies or integrated device manufacturers (IDMs).\n*   **Foundry Services:** Offering this advanced packaging process as a service to chip designers.\n*   **IP Licensing:** Licensing the patent to other semiconductor manufacturers or packaging houses.\n*   **Product Differentiation:** Companies developing their own products (e.g., AI accelerators, mobile processors) can leverage this technology to create differentiated offerings with superior performance and form factor, commanding premium pricing.\n\n**Strategic Positioning:**\nAdopting this technology allows companies to strategically position themselves as leaders in advanced packaging and 3D integration. It enables them to move up the value chain, offering solutions that are critical for emerging technologies. For instance, in AI hardware, this innovation could facilitate the creation of high-bandwidth memory (HBM) stacks and multi-chip modules (MCMs) that are essential for accelerating neural network training and inference. In mobile, it supports the continuous push for compact, feature-rich devices.\n\n**ROI Projections:**\nThe return on investment for implementing this patent can be substantial. Reduced manufacturing costs (due to higher yield and streamlined processes), coupled with the ability to create higher-value, differentiated products, translates into improved profit margins. Furthermore, the ability to meet market demands for miniaturization and performance faster than competitors can lead to increased market share and brand leadership. Early adoption and mastery of this technology could secure a significant competitive moat, yielding long-term financial benefits in a capital-intensive industry.","faqs":[{"answer":"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same (US-9853012) is a patent describing a groundbreaking method for creating advanced, high-density semiconductor packages. Essentially, it details a sophisticated way to stack multiple computer chips vertically, allowing them to communicate much more efficiently than traditional methods.\n\nThe core innovation involves a hybrid packaging approach that combines wafer-level and chip-level fabrication techniques. This means that instead of just laying chips flat or using complex, costly vertical drilling methods, this patent outlines a modular system where chips are stacked in pre-assembled units and then integrated into a larger, multi-tier package.\n\nA key feature of this technology is the use of 'through electrodes' – tiny, direct electrical pathways that pass vertically through the stacked chips. These electrodes act like express elevators for electrical signals, significantly reducing the distance and time it takes for data to travel between different layers of chips, thereby boosting overall performance and efficiency.","question":"What is Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same?"},{"answer":"The method described in Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same involves several precise steps to achieve its high-density, high-performance chip stacking. It begins by forming a 'wafer-level package' where an initial set of semiconductor chips are stacked on a base chip and then encapsulated.\n\nConcurrently, 'chip-level packages' are created. These are smaller, modular stacks of chips that can be pre-fabricated and tested. The brilliance of this approach lies in then stacking a plurality of these chip-level packages onto the back surface of the wafer-level package's base chip, forming a highly integrated, multi-tier structure.\n\nA critical step is the meticulous polishing of the mold layer and the stacked chips. This process is designed to expose pre-fabricated 'through electrodes' embedded within the chips. Once exposed, 'outer electrodes' are formed on the polished surfaces, directly connecting to these through electrodes. This creates robust, short, and highly efficient vertical electrical pathways throughout the entire stacked package.","question":"How does Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same work?"},{"answer":"The Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same patent addresses several critical problems in modern electronics manufacturing. Primarily, it tackles the challenge of increasing chip density and performance in devices that are constantly shrinking in size.\n\nTraditional 2D chip design is reaching its physical limits, making it difficult to pack more functionality onto a single plane. Older 3D stacking methods, such as wire bonding, were bulky and slow, while Through-Silicon Via (TSV) technology, though effective, is often complex, costly, and can introduce manufacturing yield issues. These limitations hindered the development of thinner, faster, and more energy-efficient devices.\n\nThis innovation solves these issues by providing a scalable, high-density, and high-performance 3D packaging solution. By creating direct, short vertical interconnects via through electrodes and combining modular stacking techniques, it overcomes the bottlenecks of prior art, enabling the creation of compact, powerful, and reliable electronic components for next-generation devices.","question":"What problem does Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same solve?"},{"answer":"The patent US-9853012, titled \"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same,\" was filed on 2016-01-29 and published on 2017-12-26. The specific inventors are not provided in the prompt data, nor is the assignee. However, such advanced semiconductor packaging innovations typically originate from leading global semiconductor companies or research institutions deeply involved in microelectronics fabrication and assembly.\n\nThese organizations invest heavily in research and development to push the boundaries of chip technology, recognizing the critical role of packaging in achieving higher integration densities and improved electrical performance. The development of through electrode technology represents a collaborative effort across various engineering disciplines, including materials science, electrical engineering, and manufacturing process development. The impact of this patent highlights the ongoing drive by innovators to solve complex challenges in semiconductor integration.","question":"Who invented Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same?"},{"answer":"The Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same offers several significant benefits that are crucial for the advancement of modern electronics:\n\nFirst, it enables **ultra-high integration density**. By combining wafer-level and chip-level stacking with direct vertical interconnects, this technology allows significantly more active components to be packed into a smaller physical footprint. This is vital for miniaturization in devices like smartphones and wearables.\n\nSecond, it provides **superior electrical performance**. The direct 'through electrodes' create very short electrical pathways between stacked chips, drastically reducing parasitic capacitance and inductance. This translates to faster data transfer rates, lower power consumption, and improved signal integrity, making devices quicker and more energy-efficient.\n\nThird, the method offers **improved manufacturing efficiency and scalability**. The modular nature of chip-level packages and the precise, controlled polishing process for electrode exposure can lead to higher manufacturing yields and potentially lower unit costs compared to some more complex prior art 3D packaging techniques. This makes advanced packaging more accessible for mass production.","question":"What are the key benefits of Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same?"},{"answer":"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same differentiates itself from prior art methods like wire bonding, flip-chip, and even some Through-Silicon Via (TSV) implementations through several key innovations.\n\nUnlike **wire bonding**, which uses peripheral wires, this patent employs direct vertical 'through electrodes', offering vastly higher interconnect density and significantly shorter signal paths. Compared to **flip-chip**, which is primarily a 2.5D solution, this invention provides true 3D stacking with direct vertical communication between multiple active layers.\n\nAgainst **TSV technology**, this patent's unique hybrid approach of combining wafer-level and chip-level packages, along with the precise polishing to expose pre-fabricated through electrodes, potentially offers a more streamlined and cost-effective manufacturing flow. While TSVs involve complex etching and filling processes, this invention leverages a different method of creating and accessing vertical interconnects, which could lead to better yields and simpler integration for multi-tier heterogeneous stacks. It focuses on direct, robust connections that minimize manufacturing complexity while maximizing performance.","question":"How is Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same different from prior art?"},{"answer":"The Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same patent is set to have a transformative impact across a wide array of industries that rely on advanced electronics.\n\nIn **Consumer Electronics**, it will enable the development of thinner, lighter, and more powerful smartphones, tablets, wearables, and augmented/virtual reality devices, driving the next wave of innovation in personal technology. For **High-Performance Computing (HPC) and Artificial Intelligence (AI)**, this technology will facilitate the creation of denser, faster, and more energy-efficient processors and memory modules, accelerating AI model training and complex data analytics.\n\n**Automotive Electronics** will benefit from more compact and reliable electronic control units (ECUs) and sensor fusion platforms crucial for autonomous driving and advanced safety systems. The **Internet of Things (IoT)** sector will see the proliferation of smaller, smarter, and more capable sensors and edge devices, extending connectivity and intelligence to new applications. Additionally, **Medical Devices** will leverage this for smaller, more sophisticated implantables and diagnostic tools, and **Aerospace & Defense** for high-reliability, compact systems.","question":"What industries will Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same impact?"},{"answer":"The patent titled \"Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same\" was filed on **January 29, 2016**. It was subsequently published as US-9853012 on **December 26, 2017**.\n\nThe filing date marks the initial submission of the invention to the patent office, establishing its priority. The publication date signifies when the patent application became publicly accessible, allowing the broader industry and research community to review the disclosed technology. These dates are crucial for understanding the timeline of the innovation and its position within the landscape of semiconductor packaging advancements. The period between filing and publication allows for examination and potential revisions by the patent office.","question":"When was Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same filed/granted?"},{"answer":"The commercial applications of Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same are extensive, driven by the universal demand for high-performance, miniaturized, and energy-efficient electronics.\n\nOne primary application is in **mobile processors and memory modules** for smartphones and tablets, enabling thinner form factors, faster app performance, and extended battery life. In **AI accelerators**, this technology can create compact, powerful chip stacks essential for both cloud-based AI training and edge AI inference in devices. For **wearable technology**, it allows for highly integrated, low-power modules that fit into tiny form factors.\n\nFurthermore, in **automotive electronics**, it can be used for advanced driver-assistance systems (ADAS) and infotainment units, requiring high reliability and performance in compact spaces. **IoT devices**, from smart home sensors to industrial monitoring equipment, will benefit from the ability to pack more functionality into smaller, more robust packages. This patent provides a foundational technology for any product requiring significant computational power within tight spatial or power constraints.","question":"What are the commercial applications of Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same?"},{"answer":"The principles outlined in Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same lay the groundwork for exciting future developments in semiconductor packaging and beyond.\n\nWe can anticipate further optimization of the **hybrid stacking process**, leading to even higher integration densities and potentially more layers of stacked chips. Research will likely focus on integrating novel **thermal management solutions** directly into these compact packages to address heat dissipation challenges, potentially through micro-fluidic cooling or advanced thermal interface materials. The flexibility of this approach also suggests a future where **heterogeneous integration** becomes even more seamless, allowing disparate functionalities (e.g., logic, memory, sensors, photonics) from different manufacturing processes to be combined into highly optimized 'chiplet' systems.\n\nExpect advancements in **manufacturing yield and cost reduction**, making this sophisticated packaging technology more accessible for a wider range of applications. Ultimately, this patent will contribute to the realization of truly integrated 'systems-in-a-package' that are not just smaller and faster, but also more intelligent, energy-efficient, and capable of enabling entirely new categories of electronic devices.","question":"What are the future developments expected for Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same?"}],"topics":["semiconductor packages","through electrodes","chip stacking","3D integration","wafer-level package","relentless","pursuit","moore"],"tech_cluster":null},"seo":{"title":"Semiconductor Packages with Through Electrodes - US-9853012","description":"Discover Semiconductor Packages Having Through Electrodes and Methods of Fabricating the Same. This patent details advanced chip stacking for ultra-dense, high-performance electronics.","keywords":["semiconductor packages","through electrodes","chip stacking","3D integration","wafer-level package","advanced packaging","microelectronics","high-density interconnects","semiconductor manufacturing","US-9853012 patent","electronics miniaturization","vertical interconnects","chip-level package","semiconductor fabrication","packaging innovation"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9853012","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9853012","citation_suggestion":"Patentable. \"Semiconductor packages having through electrodes and methods of fabricating the same\" (US-9853012). https://patentable.app/patents/US-9853012","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9853012","json":"https://patentable.app/api/llm-context/US-9853012","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:39:22.680Z"}