{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9853036","patent":{"patent_number":"US-9853036","title":"Asymmetric dense floating gate nonvolatile memory with decoupled capacitor","assignee":null,"inventors":[],"filing_date":"2014-09-17T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["G06F","G06F","G11C"],"num_claims":16,"abstract":"A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s."},"analysis":{"summary":"The patent, \"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor\" (US-9853036), introduces a significant advancement in nonvolatile memory (NVM) bitcell architecture. Its core innovation lies in incorporating one or more active regions that are capacitively coupled to the floating gate, yet are distinctly separated from both the source and the drain terminals. This novel decoupling mechanism addresses a critical challenge in NVM design: achieving precise and efficient control over the floating gate voltage.\n\nThe primary problem this invention solves is the inefficiency and physical overhead associated with traditional NVM programming. Existing bitcells often rely on power-hungry and space-consuming charge pumps to facilitate hot-electron injection (CHEI or IHEI) for programming. By providing improved control over the floating gate voltage, this technology enables CHEI/IHEI to be performed with much higher efficiency, thereby reducing or even eliminating the need for these auxiliary charge pumps.\n\nThe key technical approach involves strategically placing capacitors that are dedicated to controlling the floating gate, independent of the main current paths. This allows for a more direct and efficient manipulation of the floating gate's potential. Furthermore, the patent describes constructing these bitcells in pairs, a clever technique that further reduces the overall space requirements, effectively mitigating any potential footprint increase from the additional capacitors.\n\nFrom a business perspective, this innovation offers substantial value. It leads to the development of smaller, more power-efficient, and potentially lower-cost NVM devices. Reduced reliance on charge pumps simplifies manufacturing and lowers bill-of-materials. The technology also provides operational flexibility, allowing the bitcell to be programmed via CHEI/IHEI or band-to-band tunneling (BTBT) depending on applied voltages, offering adaptability for diverse applications. The market opportunity is vast, spanning mobile devices, IoT, embedded systems, and enterprise storage, all of which demand increasingly compact and energy-efficient memory solutions.","layman_explanation":"For business professionals navigating the rapid advancements in technology, understanding the core innovations driving the market is crucial, even without delving into deep technical jargon. The patent, \"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor,\" represents one such innovation that promises to significantly impact the future of digital storage.\n\n**1. What Problem Does This Solve?**\nAt its heart, this patent addresses the persistent challenge in creating smaller, faster, and more energy-efficient nonvolatile memory (NVM). NVM is the type of memory that retains data even when power is off – think of your phone's storage or a solid-state drive (SSD). A key process in NVM is 'programming' or writing data to a memory cell. Traditionally, this process often requires a component called a 'charge pump,' which boosts voltage to make the programming efficient. While effective, these charge pumps are like extra engines on a small car: they take up valuable space on the silicon chip, consume a lot of power, and add to the overall cost and complexity of manufacturing the memory. This limits how small and energy-efficient memory chips can become, posing a significant hurdle for devices demanding compact, long-lasting power solutions like IoT devices, wearables, and advanced mobile electronics.\n\n**2. How Does It Work?**\nThis innovation introduces a clever architectural change to the fundamental memory cell. Instead of relying solely on the main connections (source and drain) to influence the floating gate (the part that stores the data), the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor adds dedicated, small 'helper' capacitors. Imagine the floating gate as a sensitive switch. In old designs, you'd use a big, powerful lever (the charge pump) to flip it. In this new design, these 'decoupled capacitors' act like precision micro-levers, allowing for much finer and more direct control over the switch. Because you have this precise control, you can flip the switch (program the cell) with much less force and energy, often eliminating the need for that big, power-hungry main lever. This leads to a more streamlined and efficient operation. What's more, the patent even suggests ways to arrange these memory cells in pairs, making them even more compact and efficient, offsetting the space used by these new helper capacitors. This flexibility also means the memory can be programmed in different ways depending on what's most efficient for a given task, like choosing between a quick, light touch or a slightly stronger, more stable push.\n\n**3. Why Does This Matter?**\nFor businesses, the implications are substantial. Firstly, it enables the creation of memory chips that are physically smaller. This is critical for miniaturized devices, allowing for sleeker product designs or packing more functionality into existing form factors. Secondly, the reduced reliance on charge pumps means significantly lower power consumption, translating to longer battery life for portable electronics and reduced energy costs for data centers. Thirdly, the simplified peripheral circuitry can lead to lower manufacturing costs and potentially higher yields, improving profit margins. Companies leveraging this technology could gain a significant competitive edge by offering superior memory performance, smaller footprints, and better power efficiency. It opens doors to new product categories and enhances existing ones, aligning perfectly with the market's demand for 'more performance in less space and with less power.' This innovation offers a tangible pathway to address the growing data storage needs of a connected world.\n\n**4. What's Next?**\nThis technology is poised to influence the next generation of embedded memory, high-performance computing, and edge AI devices. As the demand for processing power and data storage at the 'edge' (closer to where data is generated) grows, compact and ultra-low-power NVM solutions become indispensable. Expect to see this approach integrated into future System-on-Chip (SoC) designs, enabling more powerful and efficient smart devices, autonomous systems, and advanced enterprise solutions. For investors, this represents a technology with strong potential for market adoption and long-term value creation in the semiconductor industry.","technical_analysis":"The patent \"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor\" (US-9853036) presents a sophisticated architectural modification to the conventional nonvolatile memory (NVM) bitcell, fundamentally altering the mechanism of floating gate voltage control and programming efficiency. This technical analysis delves into the structural innovations, operational principles, and performance implications.\n\n**Technical Architecture and Innovation:**\nThe core of this invention is an NVM bitcell comprising a floating gate, a control gate, source, and drain terminals, but crucially, it introduces one or more active regions capacitively coupled to the floating gate that are *separated* from both the source and the drain. In traditional floating-gate NVMs, the floating gate's potential is primarily influenced by the control gate and channel interactions. The decoupled capacitors in this patent provide an independent, dedicated pathway to modulate the floating gate potential. This separation allows for a much finer and more direct electrical control over the floating gate, reducing parasitic influences from the source and drain regions during critical operations.\n\n**Implementation Details and Algorithm Specifics:**\nThe improved control over the floating gate voltage directly facilitates enhanced efficiency of hot-electron injection (CHEI or IHEI) mechanisms. In conventional designs, achieving the precise high voltage necessary for efficient electron injection onto the floating gate often necessitates a charge pump. This peripheral circuitry adds complexity, consumes significant die area, and impacts power efficiency. The present invention, by leveraging the decoupled capacitors, can achieve the required floating gate potential with lower external voltage swings or with reduced reliance on charge pumps. This suggests an optimization in the programming algorithm, where the voltage sequence applied to the control gate and the decoupled capacitor(s) can be precisely tailored to generate the optimal electric field for injection, rather than relying solely on the control gate and channel bias.\n\nFurthermore, the patent describes that the bitcells may be constructed in pairs. This suggests a layout optimization strategy where two adjacent bitcells might share certain peripheral elements or be arranged in a way that minimizes the overall silicon footprint, effectively offsetting the area consumed by the additional decoupled capacitors. This pairing could involve shared word lines, bit lines, or control lines for the decoupled capacitors themselves, enhancing density.\n\n**Performance Characteristics and Operational Flexibility:**\nOne of the most compelling aspects of this innovation is its operational flexibility. The bitcell can be programmed and erased using either CHEI/IHEI or band-to-band tunneling (BTBT), depending on the specific voltages applied at the source, drain, and the decoupled capacitor(s). This dual-mode capability is highly valuable. CHEI/IHEI typically offers good endurance and precise threshold voltage control, while BTBT can provide faster erase times and lower power consumption for specific write/erase cycles. The ability to dynamically switch between these mechanisms allows memory controllers to optimize for different workloads, balancing speed, endurance, and power consumption as required by the application.\n\n**Integration Patterns and Code-Level Implications:**\nFrom an integration standpoint, the reduced need for complex charge pump circuitry simplifies the overall NVM macro design. This can lead to smaller memory blocks, easier integration into System-on-Chip (SoC) designs, and potentially faster memory access times due to simpler peripheral logic. At a code level, the memory controller firmware would need to manage the voltage sequences for the decoupled capacitors and adapt the programming/erase algorithms based on the chosen operation mode (CHEI/IHEI vs. BTBT), potentially involving more sophisticated state machines but ultimately leading to more optimized memory performance for various use cases. This patent represents a significant step towards more efficient, compact, and versatile nonvolatile memory solutions.","business_analysis":"The \"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor\" patent (US-9853036) represents a pivotal innovation with substantial commercial implications for the semiconductor and electronics industries. Its core technical advancements translate directly into compelling business value, positioning it to capture significant market share in the rapidly expanding nonvolatile memory (NVM) sector.\n\n**Market Opportunity Size:** The global nonvolatile memory market is projected to grow significantly, driven by demand from mobile devices, IoT, automotive, data centers, and AI/ML applications. All these sectors prioritize higher density, lower power consumption, and improved performance. This patent directly addresses these critical requirements, making its underlying technology highly relevant across a multi-billion-dollar market. Any technology that can offer a tangible advantage in these metrics stands to unlock immense value.\n\n**Competitive Advantages:** This innovation provides several distinct competitive advantages. Firstly, by reducing or eliminating the need for large charge pumps, it enables the creation of NVM bitcells that are inherently smaller and more power-efficient than much of the prior art. This translates to higher memory density per chip, a crucial factor in competitive product differentiation. Secondly, the enhanced control over the floating gate voltage allows for more efficient programming (CHEI/IHEI), potentially leading to faster write speeds and improved endurance, both key performance indicators for NVM. Thirdly, the operational flexibility, allowing for both CHEI/IHEI and BTBT programming, provides product designers with a versatile tool to optimize memory characteristics for specific applications, offering a customizable performance profile that competitors might struggle to match.\n\n**Revenue Potential and Business Models:** Companies licensing or implementing this technology could see increased revenue through several avenues: 1) **Premium Products:** Offering NVM chips with superior power efficiency, smaller footprint, and higher performance at a premium. 2) **Cost Reduction:** Lower manufacturing costs due to simpler peripheral circuitry (fewer/smaller charge pumps) and potentially higher yields from a more robust design. 3) **New Market Entry:** Enabling the development of NVM for ultra-low-power edge devices or highly integrated SoCs where existing NVM solutions are too large or power-hungry. Business models could include direct sales of NVM components, licensing the patented technology to other semiconductor manufacturers, or integrating it into proprietary SoC designs for internal product differentiation.\n\n**Strategic Positioning:** This technology positions adopting companies as leaders in next-generation NVM solutions. It offers a strategic hedge against competitors reliant on older, less efficient NVM architectures. For device manufacturers, access to this technology means creating products with longer battery life, sleeker form factors, and faster responsiveness, enhancing their competitive edge in consumer electronics and industrial applications. It aligns perfectly with trends towards 'more-than-Moore' integration and energy-efficient computing.\n\n**ROI Projections:** The return on investment for adopting or licensing the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor can be significant. Reduced power consumption directly translates to lower operational costs for data centers and longer battery life for portable devices, both highly valued by end-users. The potential for higher density means more storage in the same footprint, or the same storage in a smaller footprint, leading to better product differentiation and potentially higher selling prices. Furthermore, simplified manufacturing processes could yield cost savings in production, accelerating time-to-market and enhancing profitability. This patent provides a clear path to developing NVM products that are superior in key performance metrics while potentially reducing overall system costs.","faqs":[{"answer":"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor (US-9853036) is a patented innovation in nonvolatile memory (NVM) bitcell design. It introduces a novel architecture where one or more active regions are capacitively coupled to the floating gate but are distinctly separated from both the source and the drain terminals of the bitcell. This unique separation allows for a much finer and more efficient control over the floating gate's voltage, which is crucial for storing data persistently.\n\nThis technology represents a significant departure from traditional NVM designs, which often rely on more indirect methods of floating gate control. By decoupling these capacitive elements, the invention optimizes the programming and erase mechanisms of the memory cell. It aims to address long-standing challenges related to memory density, power consumption, and operational efficiency.\n\nEssentially, the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor provides a smarter, more precise way to manage the electrical charges that represent data within a memory cell. This leads to a more robust and adaptable memory solution, poised to impact a wide range of electronic devices requiring compact and energy-efficient storage.","question":"What is Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor?"},{"answer":"The Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor works by introducing dedicated capacitive elements that are isolated from the main current path (source and drain) but are strategically linked to the floating gate. The floating gate is where electrons are stored to represent a binary '0' or '1'. In traditional NVM, the voltage on the floating gate is primarily influenced by the control gate and the channel beneath it.\n\nThis invention adds a new, independent control mechanism. These decoupled capacitors allow for a direct and precise modulation of the floating gate's potential. This enhanced control makes the process of hot-electron injection (CHEI or IHEI), a common method for programming NVM cells, significantly more efficient. The precise voltage manipulation means that the memory cell can be programmed with less energy and often without the need for large, power-hungry charge pumps typically used in older designs.\n\nFurthermore, the patent describes that these bitcells can be constructed in pairs, which helps to optimize the physical layout and reduce the overall space requirements. The technology also offers operational flexibility, allowing the bitcell to be programmed using either CHEI/IHEI or band-to-band tunneling (BTBT), depending on the specific voltages applied to the source, drain, and the decoupled capacitors, providing adaptability for various performance needs.","question":"How does Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor work?"},{"answer":"The Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor solves several critical problems inherent in traditional nonvolatile memory (NVM) designs, particularly concerning efficiency, size, and power consumption. A primary issue in existing NVM is the reliance on charge pumps to generate the high voltages necessary for efficient hot-electron injection (CHEI or IHEI) during programming cycles.\n\nCharge pumps consume significant silicon area, add to the overall power budget of the memory chip, and increase manufacturing complexity and cost. This patent addresses this by enabling CHEI/IHEI to be performed with much higher efficiency due to superior control over the floating gate voltage. This significantly reduces or even eliminates the need for these bulky charge pumps.\n\nConsequently, the invention leads to smaller bitcell sizes, lower power consumption, and simpler peripheral circuitry. It mitigates the trade-offs between memory density, performance, and energy efficiency that have long challenged the semiconductor industry, paving the way for more compact, powerful, and sustainable electronic devices.","question":"What problem does Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor solve?"},{"answer":"The patent US-9853036, titled \"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor,\" does not list the inventors or assignee in the provided abstract. Patent filings typically include this information in the full document. However, the innovation itself is a product of advanced semiconductor research and development, likely stemming from a team of engineers and scientists focused on pushing the boundaries of nonvolatile memory technology.\n\nSuch breakthroughs are often the result of extensive collaboration within corporate R&D departments or specialized memory technology firms. The inventors would be individuals credited for conceiving the specific architectural modifications and operational principles described in the patent claims. Without the full patent document, specific names cannot be provided here.\n\nThe absence of assignee information in the provided abstract is also common in simplified data extractions. The assignee is the entity (e.g., a company or institution) that owns the patent rights. This information would be readily available in the complete patent record.","question":"Who invented Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor?"},{"answer":"The Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor offers several transformative benefits for nonvolatile memory (NVM) technology and its applications.\n\nFirstly, it enables **superior power efficiency** by significantly reducing or eliminating the need for power-hungry charge pumps. This directly translates to longer battery life for portable devices like smartphones and IoT sensors, and lower operational costs for data centers. Secondly, the innovation leads to **smaller bitcell sizes and higher memory density**. By streamlining the programming circuitry and allowing for paired bitcell construction, it maximizes the amount of data that can be stored in a given physical space, crucial for miniaturized electronics.\n\nThirdly, it provides **enhanced control over the floating gate voltage**, leading to more precise and efficient programming operations. This can result in faster write speeds and potentially improved endurance. Lastly, the technology offers **operational flexibility**, supporting both hot-electron injection (CHEI/IHEI) and band-to-band tunneling (BTBT) programming modes. This adaptability allows designers to optimize memory characteristics for specific application requirements, balancing speed, power, and endurance as needed. These benefits collectively position the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor as a significant advancement in memory technology.","question":"What are the key benefits of Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor?"},{"answer":"The Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor fundamentally differs from prior art in its approach to floating gate voltage control and programming efficiency. Traditional floating-gate NVM designs primarily rely on the control gate and channel interactions to manipulate the floating gate potential. While effective, this often necessitates the use of charge pumps to generate the high voltages needed for efficient hot-electron injection (CHEI/IHEI).\n\nThe key distinction of this innovation is the introduction of active regions capacitively coupled to the floating gate that are *separated* from both the source and the drain. This creates an independent and more direct pathway to control the floating gate's voltage. Prior art generally lacks this dedicated, decoupled capacitive control, leading to less precise voltage modulation and a greater dependency on charge pumps.\n\nThis architectural difference allows the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor to perform CHEI/IHEI with much higher efficiency, often reducing or eliminating the need for charge pumps, which are a hallmark of older NVMs. This results in smaller bitcells, lower power consumption, and greater operational flexibility (e.g., dual-mode programming) that are not typically found in conventional NVM architectures. It represents a shift from a more generalized control mechanism to a highly specialized and efficient one.","question":"How is Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor different from prior art?"},{"answer":"The Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor is poised to impact a wide array of industries that rely heavily on advanced nonvolatile memory (NVM) solutions. Its core benefits of smaller size, lower power consumption, and enhanced efficiency make it particularly relevant for sectors demanding cutting-edge memory technology.\n\nKey industries include **mobile electronics** (smartphones, tablets, wearables), where longer battery life and thinner form factors are paramount. The **Internet of Things (IoT)** will also see significant impact, as billions of edge devices require ultra-low-power, compact, and robust memory for extended operation in remote or battery-constrained environments. **Automotive electronics** will benefit from more reliable and efficient embedded NVM for advanced driver-assistance systems (ADAS) and infotainment.\n\nFurthermore, **enterprise storage** (SSDs for data centers) can leverage higher memory density and power efficiency to build more sustainable and cost-effective cloud infrastructure. The **AI and machine learning** sector, particularly for edge AI applications, will find value in compact, fast, and energy-efficient memory for on-device inference. Essentially, any industry utilizing embedded systems or requiring high-performance, compact, and energy-efficient persistent storage will be influenced by this innovation.","question":"What industries will Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor impact?"},{"answer":"The patent for Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor, identified as US-9853036, was officially **filed on September 17, 2014**. The journey from filing to grant can often take several years, involving examination, revisions, and overcoming prior art objections.\n\nThis particular patent was subsequently **published and granted on December 26, 2017**. This publication date marks when the full details of the invention became publicly available and the patent rights were formally conferred. The period between filing and grant indicates the time taken for the U.S. Patent and Trademark Office (USPTO) to review and approve the claims of the invention.\n\nThese dates are important for understanding the timeline of the technology's development and its legal protection. The 2017 grant date means that the technology has been protected and available for licensing or commercialization since then, influencing memory development in the years that followed.","question":"When was Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor filed/granted?"},{"answer":"The commercial applications of Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor are vast and diverse, stemming directly from its ability to deliver smaller, more power-efficient, and versatile nonvolatile memory (NVM).\n\nIn **consumer electronics**, this technology can lead to next-generation smartphones, smartwatches, and other portable devices with extended battery life and sleeker designs due to reduced memory footprint. For the **Internet of Things (IoT)**, it enables the creation of ultra-low-power sensors and edge devices that can operate autonomously for years, expanding the reach and capabilities of connected environments.\n\nIn **automotive**, it can support advanced in-car systems, autonomous driving platforms, and robust data logging, where reliability and efficiency are paramount. **Enterprise and data center storage** can benefit from higher-density solid-state drives (SSDs) that consume less power, leading to more sustainable and cost-effective cloud infrastructure. Furthermore, for **embedded systems and industrial control**, it offers robust and efficient memory for critical applications where space and power are severely constrained. The operational flexibility also allows for tailored memory solutions, opening doors for specialized applications in areas like medical devices or defense.","question":"What are the commercial applications of Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor?"},{"answer":"Future developments for the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor are expected to build upon its foundational architectural advantages, further enhancing its capabilities and expanding its applications.\n\nOne key area will likely be **integration with advanced process nodes**. As semiconductor manufacturing scales down, the principles of decoupled capacitance can be further optimized for even smaller feature sizes, pushing memory density and efficiency to new limits. We can also anticipate **hybrid memory architectures** where this NVM is combined with other memory types (e.g., DRAM, SRAM) on a single chip, creating highly optimized memory subsystems for specific workloads like AI accelerators or high-performance computing.\n\nFurther **refinement of control algorithms** for the decoupled capacitors will likely emerge, allowing for even more precise voltage manipulation and potentially unlocking new programming/erase modes or enhancing endurance. The **adoption in 3D stacking technologies** is also a strong possibility, where the compact nature of the bitcell and reduced peripheral circuitry could enable truly dense and high-bandwidth 3D NVM arrays. Ultimately, the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor is expected to become a cornerstone for the development of more intelligent, autonomous, and energy-conscious computing systems across all sectors.","question":"What are the future developments expected for Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor?"}],"topics":["Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor","nonvolatile memory","NVM bitcell","floating gate","decoupled capacitor","relentless","demand","higher"],"tech_cluster":null},"seo":{"title":"Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor - Patent US-9853036","description":"Discover the Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor patent: smaller, more efficient NVM bitcells with decoupled capacitors. Boosts programming efficiency, reduces charge pumps, and offers flexible operation. Explore technical analysis, benefits, and market impact.","keywords":["Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor","nonvolatile memory","NVM bitcell","floating gate","decoupled capacitor","hot-electron injection","charge pump reduction","memory efficiency","semiconductor innovation","patent US-9853036","memory architecture","low-power NVM","solid-state storage"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9853036","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9853036","citation_suggestion":"Patentable. \"Asymmetric dense floating gate nonvolatile memory with decoupled capacitor\" (US-9853036). https://patentable.app/patents/US-9853036","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9853036","json":"https://patentable.app/api/llm-context/US-9853036","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:33:16.753Z"}