{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9853056","patent":{"patent_number":"US-9853056","title":"Strained CMOS on strain relaxation buffer substrate","assignee":null,"inventors":[],"filing_date":"2016-09-02T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":8,"abstract":"A set of silicon fins for n-type FinFET devices and a set of silicon germanium fins for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. Each fin in the set of silicon fins is cut forming a set of cut silicon fins having a set of vertical faces at a fin end of a respective cut silicon fin. Each fin in the set of silicon germanium fins is cut forming a set of cut silicon germanium fins having a set of vertical faces at a fin end of a respective silicon germanium fin. A set of tensile dielectric structures is formed. Each of the tensile dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures are formed. Each of the compressive dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon germanium fins to maintain compressive strain at the fin ends of the set of cut silicon fins. Another aspect of the invention is a device which is created by the method."},"analysis":{"summary":"The patent, **Strained Cmos on Strain Relaxation Buffer Substrate** (US-9853056), introduces a pivotal innovation in semiconductor manufacturing, specifically for enhancing FinFET device performance. Its core innovation lies in a method for precisely engineering strain in both n-type and p-type FinFETs on a single strain relaxation buffer (SRB) substrate.\n\nThe primary problem this invention solves is the challenge of optimizing carrier mobility in advanced FinFET devices. As transistors shrink, traditional methods of boosting performance by simply reducing size become less effective. Enhancing electron mobility in n-type silicon channels and hole mobility in p-type silicon germanium channels through controlled mechanical strain is crucial, but achieving this precisely and stably for both types on a shared substrate has been a significant hurdle.\n\nThe key technical approach involves fabricating distinct sets of silicon fins for n-type FinFETs and silicon germanium fins for p-type FinFETs on an SRB substrate. A critical step is cutting these fins to create vertical faces at their ends. Subsequently, tensile dielectric structures are strategically formed to contact the vertical faces of the silicon fins, inducing and maintaining tensile strain optimal for n-type performance. Simultaneously, compressive dielectric structures are formed to contact the vertical faces of the silicon germanium fins, maintaining compressive strain ideal for p-type performance. This dual, localized strain application dramatically improves electron and hole mobility, leading to faster and more power-efficient transistors.\n\nFrom a business perspective, this technology offers significant value. It enables the creation of next-generation microprocessors that deliver higher computational speeds with reduced power consumption, addressing critical market demands in high-performance computing, artificial intelligence, mobile devices, and IoT. This innovation provides a competitive advantage for semiconductor manufacturers by offering a scalable and robust method for enhancing device performance and potentially improving manufacturing yields.\n\nThe market opportunity is substantial, as the demand for faster, more energy-efficient chips continues to grow across virtually every technology sector. By providing a fundamental improvement in transistor performance, this patent positions itself as a key enabler for future advancements in microelectronics, promising enhanced ROI for companies that adopt or license this technology.","layman_explanation":"### 1. What Problem Does This Solve?\n\nImagine you're trying to build a super-fast highway for tiny cars (which are like electrical signals in a computer chip). For years, engineers made these highways faster by simply making them narrower and putting more lanes in a small space. This worked great, but now the lanes are so narrow, the cars are starting to bump into each other, slow down, or even get stuck. This 'traffic jam' is a major problem for modern computer chips, making them less efficient and hotter, especially in advanced 3D transistors known as FinFETs. The core business challenge is that our devices need to be ever faster and use less battery, but simply shrinking components isn't cutting it anymore. Existing solutions often struggle to make both types of 'traffic' (electrons and holes) move optimally without making the manufacturing process incredibly complex or expensive.\n\n### 2. How Does It Work?\n\n**Strained Cmos on Strain Relaxation Buffer Substrate** tackles this problem with an ingenious approach, like building a special kind of highway that actively helps cars move faster. Instead of just making the lanes narrower, this innovation physically 'tunes' the road material itself. Think of it like this: for the 'electron cars', it slightly stretches the road material, making it easier for them to glide. For the 'hole cars', it slightly compresses the road material, which also helps them speed up. This 'stretching' and 'squeezing' (called strain engineering) is done very precisely on tiny 3D structures (the FinFETs). The patent describes building these FinFETs on a special 'cushion' (a strain relaxation buffer substrate) that helps everything stay stable. Then, at the very ends of these tiny roads, special 'support beams' (dielectric structures) are put in place. Some beams are designed to stretch the electron-car roads, and others are designed to squeeze the hole-car roads. This ensures that each type of car gets its perfectly tuned road, allowing both to achieve maximum speed and efficiency on the same chip.\n\n### 3. Why Does This Matter?\n\nThis technology matters immensely because it unlocks a new level of performance and efficiency for virtually all electronic devices. By allowing transistors to switch faster and consume less power, it directly impacts the speed of your smartphone, the battery life of your laptop, the processing power of AI systems, and the energy footprint of massive data centers. For businesses, this translates into several key advantages: higher-performing products that command premium prices, reduced operational costs due to lower power consumption, and a significant competitive edge in the fiercely innovative semiconductor market. Companies adopting this approach can deliver next-generation processors that meet the escalating demands of modern applications, leading to greater market share and potentially higher profit margins. It's a fundamental improvement that sets a new bar for what's possible in microchip design.\n\n### 4. What's Next?\n\nThe **Strained Cmos on Strain Relaxation Buffer Substrate** patent is a foundational technology. We can expect to see its principles integrated into upcoming generations of processors, enabling breakthroughs in areas like edge AI, advanced robotics, and immersive virtual reality. As the demand for computational power continues to grow exponentially, innovations like this will be crucial for maintaining progress. For investors, this represents an opportunity to back companies at the forefront of silicon innovation, poised to capitalize on the next wave of technological advancement. Its impact will likely be seen in commercial products within the next 3-5 years, extending the capabilities of current FinFET technology and paving the way for even more sophisticated architectures.","technical_analysis":"The patent **Strained Cmos on Strain Relaxation Buffer Substrate** (US-9853056) details a sophisticated method for optimizing the performance of FinFET (Fin Field-Effect Transistor) devices through precise strain engineering. At its heart, this innovation addresses the critical need to enhance carrier mobility in both n-type and p-type FinFETs, which are foundational components of modern high-performance microprocessors.\n\n**Technical Architecture and Substrate Foundation:**\n\nThe system begins with the provision of a strain relaxation buffer (SRB) substrate. This SRB layer is crucial for managing lattice mismatch and reducing defect densities when integrating different semiconductor materials, particularly silicon (Si) and silicon germanium (SiGe). On this SRB substrate, two distinct sets of fins are formed: silicon fins specifically for n-type FinFET devices and silicon germanium fins for p-type FinFET devices. The choice of Si for n-type and SiGe for p-type is strategic, as Si benefits more from tensile strain for electron mobility, while SiGe benefits from compressive strain for hole mobility.\n\n**Implementation Details – Fin Cutting and Dielectric Stressors:**\n\nThe core of the invention lies in the subsequent processing of these fins. Each fin in both the silicon and silicon germanium sets undergoes a precise cutting operation. This cutting forms a set of vertical faces at the fin ends. These vertical faces are not merely structural; they are critical interfaces for the application of strain-inducing dielectric structures.\n\n1.  **Tensile Strain for n-type Si Fins:** For the silicon fins designated for n-type FinFETs, a set of tensile dielectric structures are formed. These structures are engineered to directly contact the newly created vertical faces at the fin ends. The intrinsic tensile stress within these dielectric materials (e.g., silicon nitride with high tensile stress) is transferred to the silicon lattice of the fin. This sustained tensile strain significantly enhances electron mobility within the n-channel, leading to higher drive current and faster switching speeds.\n\n2.  **Compressive Strain for p-type SiGe Fins:** Concurrently, for the silicon germanium fins designated for p-type FinFETs, a set of compressive dielectric structures are formed. These structures are designed to contact the vertical faces of the SiGe fin ends. The intrinsic compressive stress within these dielectric materials (e.g., silicon nitride with high compressive stress or silicon oxynitride) is transferred to the SiGe lattice. This maintained compressive strain boosts hole mobility within the p-channel, offering similar performance benefits for p-type devices.\n\n**Algorithm Specifics and Performance Characteristics:**\n\nThe 'algorithm' here is a fabrication sequence and material engineering strategy. The key 'algorithm' is the precise spatial and material control of strain. By localizing the strain application to the fin ends via specific dielectric materials, the invention ensures that the active channel regions receive the maximum beneficial stress. This approach minimizes unintended strain propagation into adjacent devices or undesired regions, which can often be a challenge in global strain techniques.\n\nPerformance characteristics are directly improved:\n    *   **Increased Carrier Mobility:** Both electron and hole mobility are significantly enhanced, leading to higher saturation currents ($I_{ON}$) for a given gate overdrive.\n    *   **Faster Switching Speeds:** Higher carrier velocities translate to reduced propagation delays ($t_{pd}$), enabling higher clock frequencies.\n    *   **Reduced Power Consumption:** Enhanced current drive at lower operating voltages can lead to improved energy efficiency ($I_{ON}/I_{OFF}$ ratio) and reduced dynamic power dissipation.\n\n**Integration Patterns and Code-Level Implications:**\n\nThis technology integrates seamlessly into existing FinFET fabrication processes, primarily affecting the front-end-of-line (FEOL) steps related to fin patterning, etching, and dielectric deposition. It represents an evolution in materials and process engineering rather than a radical overhaul of the entire FinFET architecture. From a design perspective, engineers utilizing this approach would benefit from updated process design kits (PDKs) that model the enhanced mobility and device characteristics, allowing for more aggressive circuit designs. While there are no direct 'code-level implications' in the software sense, the invention provides a foundational hardware improvement that directly impacts the performance ceiling for software execution, enabling more complex algorithms and faster data processing in the applications running on these advanced processors. The device itself, created by this method, is the ultimate outcome.\n\nThe **Strained Cmos on Strain Relaxation Buffer Substrate** patent provides a robust, scalable, and highly effective solution for pushing the performance envelope of FinFET devices, ensuring the continued advancement of semiconductor technology.","business_analysis":"The **Strained Cmos on Strain Relaxation Buffer Substrate** patent (US-9853056) represents a significant advancement in semiconductor technology, carrying substantial business implications across multiple high-growth sectors. Its core value proposition—enhancing FinFET performance through precise strain engineering—directly addresses critical market demands for faster, more power-efficient computing.\n\n**Market Opportunity Size:**\n\nThe global semiconductor market, valued at over $500 billion annually, is perpetually driven by the need for performance improvements. Within this, the market for advanced logic and memory, heavily reliant on FinFET technology, constitutes a large and growing segment. This innovation targets high-performance computing (HPC), artificial intelligence (AI) accelerators, data centers, mobile processors, and automotive electronics. Each of these segments is experiencing explosive growth, with AI chips alone projected to reach hundreds of billions in the coming years. By enabling superior transistor characteristics, this patent taps into the fundamental building blocks of these markets, offering a foundational competitive edge.\n\n**Competitive Advantages:**\n\nThis technology provides several distinct competitive advantages:\n\n1.  **Superior Performance-to-Power Ratio:** The optimized strain engineering leads to higher carrier mobility, translating into faster switching speeds and reduced power consumption. This is a critical differentiator in markets where energy efficiency (e.g., data centers) and battery life (e.g., mobile) are paramount.\n2.  **Manufacturing Efficiency:** By integrating both n-type silicon fins and p-type silicon germanium fins on a single strain relaxation buffer (SRB) substrate with localized dielectric strain, the invention streamlines fabrication complexity compared to more disparate or less precise strain application methods. This can lead to improved manufacturing yields and lower per-chip costs.\n3.  **Scalability and Future-Proofing:** The approach is compatible with existing FinFET architectures and offers a pathway for continued performance scaling even as traditional dimensional scaling slows. This positions adopters favorably for future generations of semiconductor nodes.\n4.  **IP Protection:** Owning a foundational patent like **Strained Cmos on Strain Relaxation Buffer Substrate** provides significant intellectual property protection, offering licensing opportunities or a strong defensive position against competitors.\n\n**Revenue Potential and Business Models:**\n\nCompanies adopting this technology, primarily leading-edge semiconductor foundries (e.g., TSMC, Samsung, Intel) and integrated device manufacturers (IDMs), can realize revenue growth through:\n\n*   **Premium Pricing:** Chips incorporating this advanced technology can command higher prices due to their superior performance and efficiency.\n*   **Market Share Gain:** Offering best-in-class processors can capture greater market share in highly competitive segments.\n*   **Licensing:** The patent holders could license the technology to other foundries or IDMs, generating substantial royalty income.\n*   **New Product Categories:** Enabling performance thresholds previously unattainable could open doors to entirely new product lines or markets.\n\n**Strategic Positioning:**\n\nStrategically, this innovation allows companies to solidify their leadership in advanced process nodes. It enables them to deliver products that meet the increasingly stringent demands of AI, 5G, and edge computing. Furthermore, it strengthens their position against competitors who may struggle with less efficient strain engineering techniques, driving innovation and setting new industry benchmarks.\n\n**ROI Projections:**\n\nThe return on investment for implementing **Strained Cmos on Strain Relaxation Buffer Substrate** would be realized through increased revenue from higher-performing products, improved manufacturing efficiency, and potential licensing income. Given the high capital expenditure in semiconductor fabrication, any technology that offers a significant and sustainable performance boost with improved yield promises a strong ROI over the lifecycle of the process node. The ability to extend the life and competitiveness of FinFET technology before migrating to entirely new architectures (like Gate-All-Around) also provides substantial economic benefits by leveraging existing infrastructure and expertise.","faqs":[{"answer":"Strained Cmos on Strain Relaxation Buffer Substrate is a patented semiconductor manufacturing technology (US-9853056) designed to significantly enhance the performance of FinFET (Fin Field-Effect Transistor) devices. It achieves this by precisely engineering mechanical strain within the active channels of both n-type and p-type FinFETs.\n\nThe invention leverages a specialized 'strain relaxation buffer' (SRB) substrate as a foundation. On this substrate, distinct silicon fins are created for n-type FinFETs and silicon germanium fins for p-type FinFETs. The core of this innovation involves cutting these fins to form vertical faces at their ends, which then serve as precise contact points for strain-inducing dielectric structures.\n\nThese dielectric structures are specifically designed: tensile (stretching) dielectric structures are applied to the silicon fins to boost electron mobility, while compressive (squeezing) dielectric structures are applied to the silicon germanium fins to enhance hole mobility. This dual, localized strain application dramatically improves the speed and efficiency of the transistors, forming the basis for faster and more power-efficient microprocessors.","question":"What is Strained Cmos on Strain Relaxation Buffer Substrate?"},{"answer":"The Strained Cmos on Strain Relaxation Buffer Substrate patent works by systematically applying specific mechanical stresses, or 'strain,' to the semiconductor channels of FinFET devices. Here's a step-by-step breakdown:\n\nFirst, a strain relaxation buffer (SRB) substrate is prepared. This specialized base layer helps in growing high-quality silicon (Si) and silicon germanium (SiGe) materials with minimal internal stress.\n\nNext, two types of fins are fabricated on this SRB substrate: silicon fins for n-type FinFETs (which primarily use electrons for conduction) and silicon germanium fins for p-type FinFETs (which use 'holes' for conduction). These materials are chosen because they respond best to different types of strain.\n\nThe crucial step involves precisely cutting the ends of these fins to create vertical faces. These faces are then used as anchors for applying strain. For the silicon fins, 'tensile' (stretching) dielectric structures are formed, which pull on the silicon lattice, making it easier for electrons to move. For the silicon germanium fins, 'compressive' (squeezing) dielectric structures are formed, which push on the SiGe lattice, making it easier for holes to move. This targeted and stable strain significantly boosts carrier mobility, leading to faster and more energy-efficient transistors.","question":"How does Strained Cmos on Strain Relaxation Buffer Substrate work?"},{"answer":"Strained Cmos on Strain Relaxation Buffer Substrate primarily solves the critical problem of optimizing carrier mobility in advanced FinFET devices, which are the fundamental building blocks of modern microchips. As transistors continue to shrink to nanometer scales, simply reducing their size no longer yields the same performance benefits as it once did. The movement of electrons and holes through the transistor channels becomes a bottleneck.\n\nExisting strain engineering techniques often faced challenges in simultaneously applying optimal and stable strain for both n-type (benefiting from tensile strain) and p-type (benefiting from compressive strain) FinFETs on a single substrate. This often led to compromises in performance for one type or increased manufacturing complexity. This patent provides a robust and integrated solution to this challenge, ensuring that both electron and hole mobility are maximized without mutual interference, thus enabling faster and more power-efficient processors for all types of electronic devices.","question":"What problem does Strained Cmos on Strain Relaxation Buffer Substrate solve?"},{"answer":"The patent for Strained Cmos on Strain Relaxation Buffer Substrate (US-9853056) does not list specific inventors in the provided data. Typically, such innovations are the result of extensive research and development efforts by teams of engineers and scientists within semiconductor companies or research institutions. While the individual inventors are not specified, the patent itself is a testament to the collective ingenuity in the field of microelectronics.\n\nThe assignee, which is the entity to whom the patent rights are transferred, is also not provided in the given data. However, patents like this are usually assigned to major semiconductor manufacturers or research consortiums that invest heavily in advanced silicon technology to push the boundaries of computing performance and efficiency. These entities drive the commercialization and integration of such innovations into the microchips that power our modern world.","question":"Who invented Strained Cmos on Strain Relaxation Buffer Substrate?"},{"answer":"The Strained Cmos on Strain Relaxation Buffer Substrate technology offers several key benefits that are crucial for the advancement of microelectronics:\n\nFirstly, it leads to **significantly enhanced transistor performance**. By precisely optimizing both tensile and compressive strain in n-type and p-type FinFETs respectively, it dramatically increases electron and hole mobility, resulting in faster switching speeds and higher drive currents. This means processors can execute tasks more quickly.\n\nSecondly, it contributes to **improved power efficiency**. Faster transistors can operate at lower voltages and reduce leakage currents, leading to less power consumption. This is vital for extending battery life in mobile devices and reducing the energy footprint of large data centers.\n\nThirdly, it offers **better manufacturability and integration**. The ability to achieve optimal strain for both device types on a single strain relaxation buffer (SRB) substrate simplifies the overall fabrication process compared to more complex, disparate methods. This can lead to higher manufacturing yields and lower production costs for advanced chips. Overall, this innovation provides a critical pathway for the continued scaling and performance enhancement of semiconductor devices.","question":"What are the key benefits of Strained Cmos on Strain Relaxation Buffer Substrate?"},{"answer":"Strained Cmos on Strain Relaxation Buffer Substrate distinguishes itself from prior art through its highly integrated yet precisely localized approach to strain engineering in FinFETs. Previous methods often involved compromises or less refined techniques.\n\nMany prior art solutions employed global strain techniques (like strained silicon-on-insulator), which were difficult to optimize for both n-type and p-type devices simultaneously, as they require different types of strain. Other methods, such as Contact Etch Stop Layers (CESL), applied strain through dielectric films over the entire device, but their effectiveness could be limited by precise control in 3D FinFET structures. Embedded SiGe offered excellent compressive strain for p-type devices but required separate, complex solutions for n-type tensile strain.\n\nThis patent's innovation lies in using a strain relaxation buffer (SRB) substrate as a stable foundation, followed by separate silicon and silicon germanium fins. Crucially, it involves cutting these fins to create specific vertical faces where highly targeted tensile dielectric structures are applied for silicon fins and compressive dielectric structures for silicon germanium fins. This ensures optimal, stable, and localized strain for each carrier type without mutual interference, a significant advancement over less precise or more complex prior art methods.","question":"How is Strained Cmos on Strain Relaxation Buffer Substrate different from prior art?"},{"answer":"The Strained Cmos on Strain Relaxation Buffer Substrate technology will have a profound impact across numerous industries that rely on high-performance and energy-efficient computing:\n\n**High-Performance Computing (HPC) and Data Centers:** Faster, more efficient processors are crucial for supercomputers, cloud infrastructure, and big data analytics, enabling quicker processing of massive datasets and complex simulations.\n\n**Artificial Intelligence (AI) and Machine Learning:** AI accelerators will benefit immensely from enhanced transistor speeds and power efficiency, leading to faster model training, more complex AI algorithms, and real-time inference at the edge.\n\n**Mobile and Consumer Electronics:** Smartphones, tablets, and wearables will see significant improvements in processing speed, responsiveness, and crucial battery life, enhancing the user experience.\n\n**Automotive Industry:** Advanced driver-assistance systems (ADAS) and autonomous vehicles require immense, reliable, and efficient computational power for real-time sensor processing and decision-making, an area where this innovation will be critical.\n\n**Internet of Things (IoT):** Edge devices, often constrained by power and size, will benefit from more efficient chips, enabling more powerful and autonomous IoT applications. Essentially, any sector driven by computational power stands to gain from this fundamental advancement in microchip technology.","question":"What industries will Strained Cmos on Strain Relaxation Buffer Substrate impact?"},{"answer":"The patent for **Strained Cmos on Strain Relaxation Buffer Substrate** (US-9853056) was filed on **September 2, 2016**. This date marks when the application was formally submitted to the patent office, initiating the examination process.\n\nThe patent was subsequently published, and the official publication date (which often coincides with the grant date in the US) was **December 26, 2017**. This is the date when the patent became publicly available and the intellectual property rights were formally recognized.\n\nThis timeline indicates a relatively swift examination process, highlighting the potential importance and novelty of the innovation within the semiconductor field. The period between filing and publication allows for the technology to be refined and for its strategic implications to be assessed before it enters the public domain and becomes a part of the broader technological landscape.","question":"When was Strained Cmos on Strain Relaxation Buffer Substrate filed/granted?"},{"answer":"The commercial applications of Strained Cmos on Strain Relaxation Buffer Substrate are extensive and span across the entire technology ecosystem that relies on advanced microprocessors. Fundamentally, any product or service requiring high computational power combined with energy efficiency can leverage this technology.\n\nKey applications include **next-generation CPUs and GPUs** for personal computers, workstations, and gaming, offering superior speed and graphical performance. In **data centers and cloud computing**, the enhanced efficiency translates to lower operational costs and a reduced carbon footprint. For **AI and machine learning**, this technology enables faster training of neural networks and more responsive AI inference at the edge.\n\nIn the **mobile sector**, this means smartphones and tablets with longer battery life, faster app performance, and improved capabilities for demanding tasks like augmented reality. The **automotive industry** will benefit from more powerful and reliable chips for autonomous driving systems and in-car infotainment. Ultimately, the Strained Cmos on Strain Relaxation Buffer Substrate innovation underpins the development of cutting-edge hardware that drives innovation in virtually every digital product and service.","question":"What are the commercial applications of Strained Cmos on Strain Relaxation Buffer Substrate?"},{"answer":"Looking ahead, the Strained Cmos on Strain Relaxation Buffer Substrate patent lays a robust foundation for numerous future developments in semiconductor technology. While the patent itself describes a specific method, its underlying principles are highly adaptable.\n\nFuture developments could involve the **optimization of dielectric materials** to achieve even higher and more stable strain levels, further boosting carrier mobility beyond current benchmarks. There's also potential for **integration with emerging transistor architectures**, such as Gate-All-Around (GAA) or nanosheet FETs, where the precise control of strain will remain critical, albeit with different geometric considerations.\n\nFurthermore, this technology could be extended to **novel channel materials** beyond silicon and silicon germanium, exploring materials with even greater inherent carrier mobility. As the industry moves towards **heterogeneous integration** and 3D stacking, the ability to precisely engineer strain in specific layers or components will become increasingly valuable. Ultimately, the Strained Cmos on Strain Relaxation Buffer Substrate innovation ensures that the quest for faster, more powerful, and energy-efficient microprocessors will continue to yield groundbreaking results for decades to come, enabling entirely new computing paradigms and applications.","question":"What are the future developments expected for Strained Cmos on Strain Relaxation Buffer Substrate?"}],"topics":["strained CMOS","FinFET technology","strain relaxation buffer","tensile strain","compressive strain","relentless","pursuit","performance"],"tech_cluster":null},"seo":{"title":"Strained Cmos on Strain Relaxation Buffer Substrate - Patent US-9853056","description":"Discover how Strained Cmos on Strain Relaxation Buffer Substrate enhances FinFET performance with optimized tensile/compressive strain. Full analysis of US-9853056 for advanced microchips.","keywords":["strained CMOS","FinFET technology","strain relaxation buffer","tensile strain","compressive strain","semiconductor patent","US-9853056","high-performance computing","silicon germanium","microchip innovation","transistor performance","dielectric structures"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9853056","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9853056","citation_suggestion":"Patentable. \"Strained CMOS on strain relaxation buffer substrate\" (US-9853056). https://patentable.app/patents/US-9853056","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9853056","json":"https://patentable.app/api/llm-context/US-9853056","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:50:25.331Z"}