{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9853101","patent":{"patent_number":"US-9853101","title":"Strained nanowire CMOS device and method of forming","assignee":null,"inventors":[],"filing_date":"2015-11-06T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":20,"abstract":"Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed."},"analysis":{"summary":"The patent, \"Strained Nanowire Cmos Device and Method of Forming\" (US-9853101), introduces a groundbreaking method for creating advanced transistor structures that significantly enhance performance and power efficiency in CMOS devices. At its core, this innovation provides a pathway to overcome the physical limitations of traditional transistor scaling by leveraging sophisticated material and structural engineering.\n\nThis patent addresses the critical industry problem of achieving continuous performance improvements in microprocessors while simultaneously reducing power consumption. Traditional planar and even early 3D transistor designs often struggle to optimally boost carrier mobility for both n-type and p-type transistors within a unified, manufacturable process flow.\n\nThe key technical approach involves the precise fabrication of transistor structures using alternating layers of two distinct epitaxial materials. A crucial step is the selective removal of one of these epitaxial materials, tailored specifically for either n-type or p-type transistor formation. This selective etching allows for the creation of optimized environments for electron and hole transport. Furthermore, the method details the removal of a bottommost layer of these materials and, most importantly, the indentation or recessing of the sidewalls of the remaining epitaxial material. These structural modifications are engineered to induce beneficial mechanical strain within the nanowire channels, which significantly increases carrier mobility.\n\nThe business value and applications of this technology are substantial. It promises to enable the development of faster, more energy-efficient microprocessors essential for next-generation computing. This includes high-performance computing, artificial intelligence accelerators, mobile devices, and data centers. The improved power-performance ratio can lead to longer battery life, reduced operational costs, and superior computational capabilities across various platforms.\n\nFrom a market opportunity perspective, this innovation positions adopters at the forefront of semiconductor technology. As demand for advanced processing power continues to surge, particularly in AI and IoT, the ability to deliver chips with intrinsically better performance characteristics offers a significant competitive advantage. This patent represents a strategic asset for semiconductor manufacturers and fabless design companies looking to differentiate their products and capture a larger share of the rapidly evolving global microchip market.","layman_explanation":"### What Problem Does This Solve?\nImagine the engine of a high-performance sports car. For years, engineers made cars faster by simply making the engine smaller and packing more power into that smaller space. This worked great, but eventually, you hit a limit – you can't make it infinitely small, and the heat generated becomes a huge problem. In the world of computer chips, we've been doing the same thing: shrinking transistors to make them faster and fit more on a chip. But like the sports car engine, we're hitting physical limits. Our devices demand more speed and power, but simply making transistors smaller isn't enough anymore, and it often leads to more power consumption, draining batteries faster or making data centers less efficient.\n\nThe core problem this patent, \"Strained Nanowire Cmos Device and Method of Forming,\" addresses is how to fundamentally make the 'roads' inside our chips better, so the tiny electrical signals (electrons and 'holes') can travel faster and more efficiently, without just making the roads shorter. It's about getting more performance per watt, a critical metric for all modern electronics, from your smartphone to massive cloud servers.\n\n### How Does It Work?\nThis innovation isn't about brute force; it's about finesse in material engineering. Think of building a tiny, microscopic skyscraper. This patent describes building transistor structures by layering two different types of building materials, one on top of the other, repeatedly. These aren't just any materials; they're special epitaxial materials that can be grown with incredible precision, almost atom by atom.\n\nNow, here's the clever part: once these layers are built, the inventors selectively remove parts of one material, depending on whether they're building an 'N-type' (for electrons) or 'P-type' (for holes) transistor. This is like carving out a very specific path for each type of electrical signal. But the real magic happens next: they remove a bottom layer and then carefully 'indent' or 'recess' the sidewalls of the remaining material. Imagine gently squeezing or stretching a soft, gummy material; it changes its internal structure, right? By doing this on a nanoscale with the nanowires, they introduce 'strain' into the material. This strain literally changes the atomic arrangement, making it much easier and faster for electrons and holes to move through the channel. It's like turning a bumpy dirt road into a super-smooth, high-speed autobahn for electrical signals, customized for each type of 'traffic'.\n\n### Why Does This Matter?\nThis technology matters because it offers a powerful solution to the semiconductor industry's most pressing challenges. By intrinsically making transistors faster and more efficient, it directly translates into: \n*   **Superior Product Performance:** Your next smartphone could be even snappier, your gaming console more immersive, and your laptop more responsive.\n*   **Energy Savings:** Faster, more efficient chips mean longer battery life for mobile devices and significantly reduced electricity consumption for data centers, leading to lower operating costs and a smaller carbon footprint.\n*   **Competitive Edge:** For chip manufacturers and tech companies, adopting this innovation provides a critical differentiator. It allows them to develop processors that outperform competitors in key areas like AI acceleration, high-performance computing, and specialized IoT devices.\n*   **Sustaining Innovation:** It helps to extend the trajectory of Moore's Law, ensuring that the pace of technological advancement in computing can continue for years to come, even as traditional scaling methods become less effective.\n\n### What's Next?\nThis patent paves the way for the next generation of microprocessors. We can expect to see companies in the semiconductor fabrication space and major chip designers exploring and integrating these principles into their future process nodes, likely within the next 3-5 years. This approach will be crucial for powering the exponential growth of AI, enabling more sophisticated autonomous systems, and delivering even more immersive digital experiences. For investors, understanding this type of fundamental innovation is key to identifying the companies that will lead the next wave of technological disruption and capture significant market share in the evolving digital economy.","technical_analysis":"The patent, \"Strained Nanowire Cmos Device and Method of Forming\" (US-9853101), outlines a sophisticated methodology for fabricating high-performance Complementary Metal-Oxide-Semiconductor (CMOS) devices, specifically focusing on Gate-All-Around (GAA) nanowire transistor architectures. The core technical innovation lies in the precise control over material composition and structural geometry to induce beneficial mechanical strain, thereby enhancing carrier mobility in both n-type and p-type devices.\n\n**Technical Architecture and Fabrication Flow:**\nThe invention commences with the formation of transistor structures using alternating layers of a first epitaxial material and a second epitaxial material. Typically, these would be materials with differing lattice constants, such as silicon (Si) and silicon-germanium (SiGe) or other III-V semiconductor combinations, grown epitaxially on a substrate. The epitaxial growth process ensures high crystallinity and precise control over layer thickness, which is critical for subsequent nanoscale patterning. These alternating layers form the foundational stack from which the nanowires will be derived.\n\n**Implementation Details – Selective Material Removal:**\nA pivotal step involves the selective removal of one of the alternating epitaxial materials. This removal is differentiated for n-type versus p-type transistors. For an n-type MOSFET, for example, the SiGe layers might be selectively etched away to leave behind Si nanowires that will form the channel. Conversely, for a p-type MOSFET, the Si layers could be selectively removed, leaving SiGe nanowires as the channel material. This selective etching is typically achieved using highly selective wet or dry etching processes that target one material over the other with high fidelity. The choice of which material to remove depends on the desired strain and carrier type, as different materials respond to strain differently to enhance electron or hole mobility.\n\n**Algorithm Specifics – Strain Engineering via Sidewall Recessing:**\nFollowing the selective removal, the patent describes two further critical modifications: the removal of a bottommost layer of the alternating materials and the indentation or recessing of the sidewalls of one of the remaining epitaxial materials. The removal of the bottommost layer serves to further isolate the nanowire channels, improving electrostatic control and reducing parasitic capacitance in GAA structures. The sidewall indentation/recessing is the primary mechanism for strain engineering. By creating specific geometric features (e.g., notches, trenches, or cavities) along the sidewalls of the active nanowire material, localized stress fields are generated. These fields apply mechanical stress (tensile or compressive) to the channel region. For n-MOS devices, tensile strain is typically induced to enhance electron mobility, while for p-MOS devices, compressive strain is applied to boost hole mobility. The precise depth, width, and shape of these recesses are critical parameters that dictate the magnitude and type of strain induced.\n\n**Integration Patterns and Performance Characteristics:**\nThis approach is designed for integration into advanced CMOS fabrication flows, likely leveraging existing FinFET or GAA process modules. The ability to independently optimize strain for n-type and p-type devices within a single fabrication platform is a significant advantage, simplifying process integration compared to disparate strain solutions. The expected performance characteristics include a substantial increase in carrier mobility, leading to higher drive currents (Ion), reduced switching delays (faster fT/fmax), and improved transconductance (gm). These improvements contribute to higher overall transistor performance and better power efficiency (lower Vdd for a given performance target, or higher performance at a given Vdd).\n\n**Code-Level Implications (Analogous to Design Parameters):**\nWhile not 'code' in the software sense, the 'code-level implications' here refer to the design parameters and models that chip designers would utilize. This includes sophisticated TCAD (Technology Computer-Aided Design) simulations to model the strain distribution and its impact on band structure and carrier transport. Device engineers would need highly accurate models for the effective mobility, threshold voltage shifts, and leakage currents resulting from the specific material choices, layer thicknesses, and recess geometries described in this patent. These models would then be incorporated into PDKs (Process Design Kits) for circuit designers to leverage the performance benefits of this strained nanowire technology in their chip designs. The precise control over epitaxial layer thicknesses and etch depths translates directly into critical design rules and process windows.","business_analysis":"The patent, \"Strained Nanowire Cmos Device and Method of Forming\" (US-9853101), represents a significant leap in semiconductor technology, with profound implications for various industries. This innovation is poised to address critical market demands for higher performance and greater energy efficiency in microprocessors, offering substantial commercial opportunities and strategic advantages.\n\n**Market Opportunity Size:**\nThe global semiconductor market is a multi-trillion-dollar industry, with logic and memory components at its core. As demand for advanced computing (AI, IoT, 5G, autonomous vehicles, high-performance computing) continues its exponential growth, the need for faster, more power-efficient processors is insatiable. This patent targets the foundational technology of these processors, meaning its potential market impact is vast, spanning every segment that relies on advanced silicon. The market for advanced process nodes (7nm and below), where this technology would be implemented, is projected to grow significantly, representing hundreds of billions of dollars in annual revenue.\n\n**Competitive Advantages:**\nThis innovation offers several distinct competitive advantages. Firstly, by enabling precise strain engineering in nanowire CMOS devices, it provides a pathway to achieve superior carrier mobility compared to conventional planar or even FinFET architectures. This translates directly into higher transistor speeds and lower power consumption, offering a significant performance-per-watt advantage. Secondly, the detailed method for selective material removal and sidewall recessing allows for optimized strain profiles for both n-type and p-type transistors within a unified process flow, simplifying manufacturing complexity compared to solutions requiring disparate processes for different transistor types. Companies adopting this technology can differentiate their products by delivering chips that are intrinsically faster and more energy-efficient, setting new benchmarks in performance.\n\n**Revenue Potential:**\nFor semiconductor foundries, licensing or implementing this technology could attract leading fabless design companies seeking cutting-edge performance. For integrated device manufacturers (IDMs), it offers a path to develop next-generation CPUs, GPUs, and specialized AI accelerators that outperform competitors. The revenue potential stems from increased market share, premium pricing for advanced performance, and reduced manufacturing costs due to optimized processes. Furthermore, the energy savings enabled by more efficient chips can translate into lower operational costs for data centers and longer battery life for mobile devices, indirectly driving demand for products incorporating this technology.\n\n**Business Models:**\nThis patent could be integrated into various business models: \n1.  **Licensing:** Semiconductor IP companies could license the technology to foundries and IDMs.\n2.  **Foundry Implementation:** Major foundries (e.g., TSMC, Samsung Foundry, Intel Foundry Services) could integrate this method into their advanced process nodes, offering it as a key differentiator to their customers.\n3.  **IDM Product Development:** Integrated device manufacturers could use this patent to design and manufacture their own proprietary high-performance processors.\n4.  **Strategic Partnerships:** Collaborations between material science companies and chip manufacturers to further optimize the epitaxial materials and etching processes.\n\n**Strategic Positioning:**\nCompanies that successfully implement the Strained Nanowire Cmos Device and Method of Forming will be strategically positioned at the forefront of the semiconductor industry. This technology is critical for leadership in segments demanding extreme performance and efficiency, such as AI/ML hardware, high-performance computing (HPC), advanced mobile platforms, and server processors. It allows for continued innovation even as traditional scaling slows, providing a long-term competitive edge.\n\n**ROI Projections:**\nThe return on investment for adopting this technology would likely be substantial. While initial R&D and capital expenditures for new process integration can be high, the resulting gains in performance and power efficiency can lead to: \n*   **Increased market share:** By offering superior products.\n*   **Higher average selling prices (ASPs):** For leading-edge components.\n*   **Cost savings:** Through optimized manufacturing processes and reduced power consumption in end products.\n*   **Accelerated product cycles:** Enabling faster time-to-market for next-generation devices. The long-term impact on brand reputation and innovation leadership would also contribute significantly to ROI.","faqs":[{"answer":"The Strained Nanowire Cmos Device and Method of Forming patent (US-9853101) describes an advanced method for fabricating next-generation transistor structures, specifically focusing on Gate-All-Around (GAA) nanowire transistors. At its core, this innovation aims to significantly boost the performance and energy efficiency of microchips.\n\nIt achieves this by meticulously engineering the internal structure of the transistors. The patent details a process that starts with creating alternating layers of different semiconductor materials. These layers are then selectively processed and sculpted to form tiny, suspended nanowires that act as the channels for electrical current.\n\nThe key breakthrough is the precise introduction of mechanical 'strain' into these nanowires. This strain, induced through careful material removal and structural modifications, alters the material's atomic properties, making it much easier and faster for electrons and holes (the carriers of electricity) to move through the transistor. This leads to faster switching speeds and reduced power consumption in the final device.\n\nEssentially, this patent provides a blueprint for building a more powerful and efficient foundation for future electronic devices by optimizing the very physics of how electricity flows within a transistor.","question":"What is Strained Nanowire Cmos Device and Method of Forming?"},{"answer":"The Strained Nanowire Cmos Device and Method of Forming works through a series of highly precise fabrication steps that leverage advanced material science and nanoscale engineering.\n\nFirst, the method involves growing alternating layers of two different epitaxial materials on a substrate. These materials are chosen for their specific properties and lattice structures. These layers form the initial stack from which the nanowires will be created.\n\nNext, a critical step is the selective removal of one of these epitaxial materials. This removal is specifically tailored depending on whether an n-type (electron-carrying) or p-type (hole-carrying) transistor is being formed. This allows for the selection of the optimal channel material for each type of carrier and helps define the nanowire structures.\n\nFinally, the patent details the removal of a bottommost layer of the alternating materials, further isolating the nanowires. Most importantly, the sidewalls of one of the remaining epitaxial materials are precisely indented or recessed. These geometric modifications introduce localized mechanical strain within the nanowire channel. This strain alters the semiconductor's band structure, significantly increasing the mobility of electrons and holes, thereby boosting transistor speed and reducing power consumption. Keywords: epitaxial layers, selective etching, sidewall recessing, mechanical strain, carrier mobility.","question":"How does Strained Nanowire Cmos Device and Method of Forming work?"},{"answer":"The Strained Nanowire Cmos Device and Method of Forming patent addresses a fundamental challenge facing the semiconductor industry: how to continue improving processor performance and energy efficiency as traditional transistor scaling reaches its physical limits.\n\nFor decades, making transistors smaller directly led to faster and more numerous components on a chip. However, at nanoscale dimensions (below 7nm), further shrinking yields diminishing returns and introduces issues like increased leakage current and manufacturing complexity. The industry needs methods to intrinsically make transistors better, not just smaller.\n\nThis innovation solves the problem of stagnating carrier mobility. By precisely inducing mechanical strain in the nanowire channels, it significantly increases how fast electrons and holes can travel through the transistor. This directly translates to faster switching speeds and lower power consumption, overcoming a major bottleneck in advanced microchip design. It provides a pathway to sustain Moore's Law and meet the growing demands for high-performance, energy-efficient computing for applications like AI, 5G, and data centers. Keywords: semiconductor bottleneck, transistor scaling, carrier mobility, power efficiency, performance improvement.","question":"What problem does Strained Nanowire Cmos Device and Method of Forming solve?"},{"answer":"The patent data provided indicates that the inventors for \"Strained Nanowire Cmos Device and Method of Forming\" (US-9853101) are not listed in this specific abstract. Typically, inventor names are detailed in the full patent document. Patents are often the result of extensive research and development efforts by teams of engineers and scientists within semiconductor companies or academic institutions.\n\nWhile specific names are not provided here, the invention itself points to expertise in advanced semiconductor fabrication, materials science, and nanoscale engineering. Such complex innovations usually require a collaborative effort from experts in fields like epitaxy, lithography, etching, and device physics to conceive and refine the methods described. The output of such teams drives the cutting edge of microchip technology. Keywords: patent inventors, semiconductor research, nanotechnology, device physics, fabrication experts.","question":"Who invented Strained Nanowire Cmos Device and Method of Forming?"},{"answer":"The Strained Nanowire Cmos Device and Method of Forming offers several transformative benefits for modern electronics:\n\nFirstly, it delivers **significantly enhanced performance**. By increasing carrier mobility through precise strain engineering, transistors can switch much faster, leading to higher clock speeds and overall greater computational power for processors in devices ranging from smartphones to supercomputers.\n\nSecondly, it provides **superior power efficiency**. Faster-moving carriers mean that transistors can achieve desired performance at lower operating voltages, or deliver more performance at the same power. This translates directly to longer battery life for mobile devices and substantial energy savings for large-scale data centers, reducing operational costs and environmental impact.\n\nFinally, this technology contributes to **continued miniaturization and innovation**. It offers a robust method to extract more performance from smaller components, enabling the development of next-generation devices for AI, IoT, and high-performance computing that would otherwise be limited by current transistor capabilities. It's a foundational step for future technological advancements. Keywords: enhanced performance, power efficiency, carrier mobility, faster processors, energy savings, miniaturization.","question":"What are the key benefits of Strained Nanowire Cmos Device and Method of Forming?"},{"answer":"The Strained Nanowire Cmos Device and Method of Forming differentiates itself from prior art (previous technologies) by its highly integrated and precise approach to strain engineering within Gate-All-Around (GAA) nanowire transistors.\n\nUnlike traditional planar MOSFETs, which suffered from poor gate control, or even FinFETs, which offered better 3D gate control but had limitations in strain optimization, this patent goes further. While GAA architectures generally improve electrostatic control by surrounding the channel with the gate, this invention specifically addresses the challenge of maximizing carrier mobility within these nanowires.\n\nThe key distinctions include: (1) The use of **alternating epitaxial layers** that allow for tailored material selection for n-type and p-type channels. (2) **Type-specific selective material removal**, enabling independent optimization of the channel material for electrons or holes, which is more precise than global strain techniques. (3) **Geometric strain induction through sidewall recessing**, a highly localized method to create specific tensile or compressive strain directly in the nanowire channel, offering finer control than bulk or contact-induced strain. These combined innovations provide superior performance and efficiency compared to earlier transistor designs. Keywords: prior art comparison, FinFETs, GAA transistors, strain engineering, selective material removal, nanoscale architecture.","question":"How is Strained Nanowire Cmos Device and Method of Forming different from prior art?"},{"answer":"The Strained Nanowire Cmos Device and Method of Forming patent has the potential to profoundly impact a wide array of industries that rely on advanced microprocessors:\n\n**High-Performance Computing (HPC) and Data Centers:** Faster, more energy-efficient processors will enable more powerful supercomputers and significantly reduce the operational costs and environmental footprint of cloud data centers, which consume vast amounts of electricity.\n\n**Artificial Intelligence (AI) and Machine Learning:** AI accelerators will become significantly more powerful and efficient, leading to faster training of complex models and more sophisticated AI capabilities in areas like autonomous vehicles, natural language processing, and medical diagnostics.\n\n**Mobile and Consumer Electronics:** Smartphones, tablets, and wearable devices will benefit from longer battery life, snappier performance, and the ability to run more demanding applications locally, enhancing user experience and enabling new device functionalities.\n\n**Automotive and IoT:** The need for powerful yet low-power processors in connected cars, smart home devices, and industrial IoT applications will be met, driving innovation in these rapidly expanding sectors. Essentially, any industry that depends on the cutting edge of silicon performance and efficiency will be positively affected by this technology. Keywords: industry impact, AI, data centers, mobile electronics, IoT, HPC, semiconductor industry.","question":"What industries will Strained Nanowire Cmos Device and Method of Forming impact?"},{"answer":"The patent, \"Strained Nanowire Cmos Device and Method of Forming\" (US-9853101), was initially filed on **November 6, 2015**. This date marks when the inventors submitted their application to the patent office, formally beginning the examination process for their innovation.\n\nFollowing a period of examination, the patent was subsequently published and granted on **December 26, 2017**. The publication date makes the details of the invention publicly available, while the granting date signifies that the patent office has recognized the novelty and inventiveness of the claims, awarding the patent holder exclusive rights to the invention for a specified period.\n\nThese dates are significant as they establish the priority of the invention and its official entry into the public domain and intellectual property landscape. They provide a timeline for when this foundational technology became a recognized and protected innovation in semiconductor manufacturing. Keywords: patent filing date, publication date, patent grant, US-9853101 timeline, intellectual property.","question":"When was Strained Nanowire Cmos Device and Method of Forming filed/granted?"},{"answer":"The commercial applications of the Strained Nanowire Cmos Device and Method of Forming are vast, touching nearly every segment of the electronics market due to its fundamental improvements in transistor performance and efficiency.\n\n**Advanced Microprocessors:** This technology will be crucial for the next generations of CPUs and GPUs, enabling higher clock speeds and greater processing power for personal computers, workstations, and gaming systems.\n\n**AI Accelerators:** Specialized chips designed for artificial intelligence workloads (e.g., in data centers, edge AI devices) will leverage this innovation to achieve unparalleled computational density and energy efficiency, accelerating the development and deployment of AI applications.\n\n**Memory Technologies:** While primarily focused on logic, the principles of strained materials can also influence advanced memory interfaces and embedded memory solutions, leading to faster data access and lower power consumption for storage.\n\n**5G/6G Communication Chips:** The high-speed and low-power characteristics are ideal for next-generation wireless communication chipsets, enabling faster data transfer and more efficient network infrastructure.\n\n**Automotive Electronics:** From advanced driver-assistance systems (ADAS) to infotainment and autonomous driving platforms, the need for powerful, reliable, and energy-efficient chips is paramount, making this technology highly relevant. Essentially, any product requiring cutting-edge semiconductor performance will be a prime candidate for incorporating this innovation. Keywords: commercial applications, AI accelerators, microprocessors, 5G chips, automotive electronics, data center efficiency, consumer electronics.","question":"What are the commercial applications of Strained Nanowire Cmos Device and Method of Forming?"},{"answer":"Looking ahead, the Strained Nanowire Cmos Device and Method of Forming is expected to drive several key future developments in semiconductor technology.\n\nFirstly, we can anticipate its **integration into mainstream advanced process nodes**. As the industry moves to 3nm and beyond, GAA nanowire architectures will become standard, and this patent's sophisticated strain engineering techniques will likely be adopted by leading foundries to maximize device performance and efficiency.\n\nSecondly, there will be **further optimization of material combinations and strain profiles**. Researchers will continue to explore novel epitaxial materials and more complex geometric designs for sidewall recessing to fine-tune strain for even greater carrier mobility and energy savings. This could lead to even more specialized transistors for specific applications.\n\nThirdly, expect **integration with emerging computing paradigms**. The foundational improvements in transistor performance could enable advancements in quantum computing interfaces, neuromorphic computing, and other beyond-CMOS technologies. This patent lays groundwork for future hybrid architectures. The long-term vision is a future where computing is not only more powerful but also more intelligent, sustainable, and capable of addressing previously unsolvable challenges. Keywords: future developments, process nodes, material optimization, quantum computing, neuromorphic computing, semiconductor roadmap, advanced CMOS.","question":"What are the future developments expected for Strained Nanowire Cmos Device and Method of Forming?"}],"topics":["strained nanowire CMOS","semiconductor patent","transistor technology","epitaxial materials","CMOS fabrication","evolution","semiconductor","technology"],"tech_cluster":null},"seo":{"title":"Strained Nanowire CMOS Device - Next-Gen Transistor Patent US-9853101","description":"Discover the Strained Nanowire CMOS Device and Method of Forming patent (US-9853101). Learn how strained nanowires boost transistor speed & power efficiency for future microchips.","keywords":["strained nanowire CMOS","semiconductor patent","transistor technology","epitaxial materials","CMOS fabrication","nanowire devices","strain engineering","high-performance computing","power efficiency","US-9853101","microchip innovation"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9853101","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9853101","citation_suggestion":"Patentable. \"Strained nanowire CMOS device and method of forming\" (US-9853101). https://patentable.app/patents/US-9853101","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9853101","json":"https://patentable.app/api/llm-context/US-9853101","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:29:00.569Z"}