{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9853151","patent":{"patent_number":"US-9853151","title":"Fully silicided linerless middle-of-line (MOL) contact","assignee":null,"inventors":[],"filing_date":"2015-09-17T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":7,"abstract":"A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide."},"analysis":{"summary":"The Fully Silicided Linerless Middle-of-line (mol) Contact patent (US-9853151) introduces a pivotal method for fabricating advanced semiconductor devices, specifically focusing on the critical source/drain contacts. The core innovation lies in creating highly efficient, low-resistance contacts by eliminating traditional resistive liner layers through a streamlined silicidation process.\n\nThe patent addresses the pervasive problem of increasing contact resistance and fabrication complexity as semiconductor features continue to shrink. In conventional designs, intermediate barrier layers often add parasitic resistance, limiting device performance and hindering further miniaturization. This invention provides a direct solution to this 'contact bottleneck' that is crucial for advanced technology nodes.\n\nTechnically, the approach involves forming source/drain regions and a gate stack, followed by an inter-level dielectric (ILD) layer. A contact pattern is then created in the ILD, which is directly filled with a silicon material. A metallic layer is subsequently deposited, and a silicidation process is performed, converting the silicon and metal into a highly conductive silicide contact. The 'linerless' aspect ensures a direct, low-resistance electrical path from the source/drain region to the interconnects.\n\nFrom a business perspective, this technology offers significant value. It enables the production of faster, more power-efficient, and denser microprocessors, which are vital for industries driven by AI, IoT, 5G, and high-performance computing. Companies adopting this method could gain a substantial competitive advantage through improved chip performance, potentially higher manufacturing yields due to simplified processing, and reduced power consumption. This innovation opens up new market opportunities by facilitating the continued scaling of semiconductor devices, ensuring the longevity of Moore's Law and unlocking further advancements in electronics.","layman_explanation":"### What Problem Does This Solve?\n\nImagine the intricate network of roads and highways within a bustling city. Now, picture that city shrinking to an unbelievably tiny scale – the size of a fingernail, but with billions of buildings (transistors) and miles of pathways (electrical connections). In our current silicon 'cities,' as these pathways, particularly the 'middle-of-line' (MOL) contacts, get smaller and smaller, they become bottlenecks. Think of it like trying to squeeze a large volume of traffic through an increasingly narrow and bumpy tunnel. This 'traffic jam' causes two major issues: increased resistance, which slows down the flow of electricity (making chips slower), and increased power consumption (draining batteries faster). Existing solutions often involve adding extra layers to these pathways to prevent problems, but these layers themselves can add to the resistance and complexity, making manufacturing harder and more expensive. This patent, the **Fully Silicided Linerless Middle-of-line (mol) Contact**, directly tackles this fundamental challenge.\n\n### How Does It Work?\n\nThis innovation offers a much smarter way to build those tiny electrical pathways. Instead of the complex, multi-layered approach that can introduce resistance, this technology streamlines the process. Conceptually, think of it as building a robust, direct bridge instead of a winding road with multiple speed bumps. The method involves: first, preparing the 'land' for our buildings (source/drain regions) and their 'fences' (gate stacks). Then, we lay down a protective 'ground cover' (inter-level dielectric layer). The crucial step is then precisely carving out the exact shape for our 'contact road' directly to the building. Instead of layering different materials for the road and its foundation, we directly fill this pathway with a special 'silicon' material. On top of this, a 'metallic' layer is added. Finally, a controlled 'baking' process (silicidation) transforms these materials into a single, incredibly strong, and highly conductive 'silicide' bridge. The key is that it's 'linerless' – meaning no extra, resistive layers are needed. It's a pure, direct, and highly efficient connection.\n\n### Why Does This Matter?\n\nThis invention holds immense significance for the entire technology landscape. By enabling ultra-low resistance and more compact electrical connections, it allows semiconductor manufacturers to continue making chips that are not only faster and more powerful but also consume less energy. This directly impacts almost every electronic device we use: your smartphone will have a longer battery life and run apps quicker; AI processors will handle complex tasks with greater efficiency; and cloud data centers will operate with reduced power demands. For businesses, this translates to significant competitive advantages. Companies that adopt this technology can produce superior products, potentially reduce manufacturing costs through simplified processes, and achieve higher yields. It's a fundamental enabler for the next generation of computing, supporting the continued growth of sectors like IoT, 5G, and advanced AI, and ensuring the longevity of Moore's Law, which predicts the doubling of transistors on a chip every two years. This innovation is a critical investment in the future of high-performance electronics.\n\n### What's Next?\n\nThe Fully Silicided Linerless Middle-of-line (mol) Contact is poised to become a standard technique in advanced semiconductor fabrication. Its adoption will likely accelerate as chip designs push further into sub-5 nanometer nodes, where traditional contact methods become increasingly unviable. We can expect to see this technology integrated into leading-edge microprocessors, memory chips, and specialized AI accelerators within the next few years. For investors, this represents an opportunity to back companies driving foundational advancements in silicon, ensuring their position at the forefront of the digital revolution. Future applications might even extend to novel materials and 3D chip architectures, where efficient vertical connections are paramount, further solidifying the importance of this streamlined approach.","technical_analysis":"The **Fully Silicided Linerless Middle-of-line (mol) Contact** patent (US-9853151) details a sophisticated method for manufacturing semiconductor devices, specifically targeting the middle-of-line (MOL) contacts. These contacts are crucial interfaces that connect the active device regions (source/drain) to the backend-of-line (BEOL) interconnects. As semiconductor technology progresses to sub-10nm nodes and beyond, managing contact resistance and ensuring reliable, scalable integration becomes paramount. This invention offers a significant advancement in this domain.\n\n**Technical Architecture and Problem Context:**\nTraditional MOL contact architectures often involve multiple layers: a metal silicide formed on the source/drain, followed by a diffusion barrier/liner layer (e.g., TiN, TaN), and then the main contact metal (e.g., Tungsten, Cobalt). While liner layers serve to prevent metal diffusion and improve adhesion, they inherently introduce additional electrical resistance and increase the overall complexity of the fabrication process. This parasitic resistance, particularly at the silicide/liner interface, becomes a critical performance bottleneck, limiting current drive and increasing RC delay in highly scaled transistors.\n\n**Implementation Details and Process Flow:**\nThis patent proposes a streamlined, 'linerless' approach to address these issues. The method involves the following sequence of steps:\n1.  **Source/Drain Region Formation:** Standard semiconductor processing techniques are used to form source/drain regions on a substrate. These are the active areas where current flows through the transistor channel.\n2.  **Gate Stack and Spacer Deposition:** A gate stack (comprising gate dielectric, gate electrode) is formed adjacent to the source/drain regions. Crucially, gate spacers are formed along the sidewalls of the gate stack. These spacers are essential for defining the gate length and protecting the gate during subsequent processing.\n3.  **Inter-Level Dielectric (ILD) Layer Application:** An ILD layer (e.g., silicon dioxide, low-k dielectric) is deposited over the entire structure, providing electrical isolation and planarization.\n4.  **Source/Drain Contact Patterning:** A lithography and anisotropic etch process is performed to selectively remove a portion of the ILD layer over the source/drain regions. This creates a precisely defined 'source/drain contact pattern' or trench, exposing the underlying source/drain material.\n5.  **Linerless Silicon Material Filling:** Here lies a key innovation: the contact pattern is then filled directly with a layer of silicon material. This silicon material is deposited such that it is in direct contact with both the source/drain region and the gate spacer. The absence of an intermediate liner layer is central to this step.\n6.  **Metallic Layer Deposition:** A metallic layer (e.g., Nickel, Cobalt, Platinum) is subsequently deposited over the newly filled silicon material.\n7.  **Silicidation Process:** Finally, a controlled thermal annealing step, known as silicidation (e.g., Rapid Thermal Annealing - RTA), is performed. During this process, the deposited metallic layer reacts with the underlying silicon material to form a highly conductive metal silicide (e.g., NiSi, CoSi2, PtSi). This silicide now constitutes the robust, low-resistance source/drain contact.\n\n**Performance Characteristics and Code-Level Implications (Material Science):**\nThe 'fully silicided' and 'linerless' nature of this contact offers superior electrical characteristics. By eliminating the resistive liner, the contact resistance (Rc) is significantly reduced, leading to:\n*   **Higher Drive Current (Ion):** Lower Rc allows for more current to flow through the transistor, enhancing device speed.\n*   **Reduced RC Delay:** The parasitic RC delay associated with the contact is minimized, which is crucial for high-frequency operation.\n*   **Improved Power Efficiency:** Lower resistance reduces power dissipation in the interconnects.\n\nFrom a material science perspective, the choice of metallic layer for silicidation is critical. Metals like Nickel, Cobalt, and Platinum form silicides with low resistivity and good thermal stability. The direct contact between the formed silicide and the underlying source/drain region ensures optimal current injection. The interaction with the gate spacer is also important for maintaining proper device isolation and preventing short circuits. This approach streamlines the process, potentially reducing defectivity and improving manufacturing yield compared to multi-layer deposition and etch schemes. The integration pattern is simpler, leading to potentially more robust and reliable devices in advanced semiconductor fabrication.","business_analysis":"The **Fully Silicided Linerless Middle-of-line (mol) Contact** patent (US-9853151) presents a compelling business proposition within the fiercely competitive semiconductor industry. This innovation directly addresses critical challenges in device scaling and performance, unlocking significant market opportunities and offering substantial competitive advantages.\n\n**Market Opportunity Size:**\nThe global semiconductor market, valued at hundreds of billions of dollars annually, is driven by the continuous demand for faster, smaller, and more energy-efficient chips. Key growth sectors like Artificial Intelligence (AI), 5G telecommunications, Internet of Things (IoT), high-performance computing (HPC), and automotive electronics all rely on advancements in silicon technology. The MOL contact is a fundamental building block in every advanced logic and memory device. Any innovation that improves contact performance and scaling directly impacts the entire ecosystem, representing a multi-billion dollar opportunity for licensing, manufacturing, and product differentiation. As chip designs push into sub-5nm nodes, the need for such optimized contacts becomes even more acute, expanding the addressable market for this technology.\n\n**Competitive Advantages:**\nThis patent provides several distinct competitive advantages for companies that adopt or license the technology:\n1.  **Superior Performance:** By significantly reducing contact resistance through a 'linerless' and 'fully silicided' approach, this invention enables chips with higher drive currents, faster switching speeds, and lower power consumption. This translates to superior product performance in end-user devices, a critical differentiator in consumer and enterprise markets.\n2.  **Advanced Scaling:** The simplified, compact nature of this contact allows for greater transistor density, facilitating the continuation of Moore's Law. Companies can achieve smaller chip footprints or pack more functionality into existing sizes, leading to cost efficiencies and enhanced capabilities.\n3.  **Manufacturing Efficiency:** Eliminating complex liner deposition and etch steps can reduce overall process complexity, thermal budget, and potentially increase manufacturing yields. Higher yields directly translate to lower per-chip manufacturing costs and improved profitability.\n4.  **Strategic Positioning:** Early adopters of this technology can establish a leadership position in advanced semiconductor manufacturing, attracting top-tier customers and talent. It positions a company at the forefront of tackling fundamental physics challenges in microelectronics.\n\n**Revenue Potential and Business Models:**\nRevenue generation from this patent could manifest through several business models:\n*   **Licensing:** Semiconductor foundries (e.g., TSMC, Samsung Foundry, Intel Foundry Services) and Integrated Device Manufacturers (IDMs) could license the technology for their fabrication processes. This would generate royalty income based on wafer volume or device count.\n*   **Internal Product Enhancement:** For IDMs, integrating this innovation into their own chip designs (e.g., CPUs, GPUs, memory) would lead to higher-performing products, commanding premium prices and increasing market share.\n*   **IP Portfolio Strengthening:** The patent enhances the overall intellectual property portfolio, providing leverage in cross-licensing agreements and strengthening market position against competitors.\n\n**Strategic Positioning and ROI Projections:**\nAdopting the Fully Silicided Linerless Middle-of-line (mol) Contact allows companies to strategically position themselves as innovators capable of overcoming physical scaling limits. The ROI is multifaceted:\n    *   **Direct ROI:** Reduced manufacturing costs due to higher yields and simpler processes.\n    *   **Indirect ROI:** Increased market share and revenue from superior products, enhanced brand reputation, and the ability to capture new market segments (e.g., ultra-low power IoT devices, extreme performance HPC).\n    *   **Long-term ROI:** Sustained ability to innovate and compete at the leading edge of semiconductor technology, ensuring relevance in a rapidly evolving industry.\n    The investment in R&D and process integration for this technology is likely to be offset by the significant performance gains and cost efficiencies realized in high-volume production, making it a highly attractive strategic move for any leading semiconductor player.","faqs":[{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact is a groundbreaking patent (US-9853151) that describes an innovative method for fabricating electrical connections within advanced semiconductor devices. Specifically, it focuses on the 'middle-of-line' (MOL) contacts, which are critical interfaces connecting the active transistor regions (source/drain) to the broader wiring network of a microchip.\n\nThe key innovation lies in its 'linerless' and 'fully silicided' design. Traditional methods often use intermediate 'liner' layers that can add resistance and complexity. This invention eliminates those liners, creating a direct, highly conductive contact through a specialized process involving silicon material, a metallic layer, and a silicidation reaction.\n\nThis technology is designed to significantly reduce electrical resistance, improve device performance, and enable greater miniaturization of semiconductor components. It's a foundational advancement crucial for the continued scaling of chips in modern electronics.","question":"What is Fully Silicided Linerless Middle-of-line (mol) Contact?"},{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact works by fundamentally streamlining the process of creating electrical connections in a microchip. Here’s a simplified breakdown of the method described in the patent:\n\nFirst, the basic structure of a transistor is formed on a semiconductor substrate, including the source/drain regions and a gate stack with its protective spacers. An insulating layer, called an inter-level dielectric (ILD) layer, is then deposited over these structures.\n\nNext, a precise pattern is etched into the ILD layer, exposing the underlying source/drain regions where the contacts need to be formed. Instead of depositing multiple barrier layers, this contact pattern is directly filled with a layer of silicon material. Following this, a metallic layer is deposited over the silicon.\n\nThe critical step is a 'silicidation' process, typically involving controlled heating. During this process, the metallic layer reacts directly with the underlying silicon material to form a highly conductive metal silicide. This silicide then forms the actual source/drain contact, providing an ultra-low resistance path for electrical current. The 'linerless' aspect means there are no intermediate resistive layers, making the connection much more efficient. Keywords: silicidation process, linerless design, silicon material, metallic layer, source/drain contact.","question":"How does Fully Silicided Linerless Middle-of-line (mol) Contact work?"},{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact solves a critical problem in advanced semiconductor manufacturing: the increasing electrical resistance and fabrication complexity of interconnections as chips continue to shrink. As transistors become smaller and more densely packed, the tiny 'middle-of-line' (MOL) contacts connecting them also shrink.\n\nIn traditional approaches, these contacts often require multiple layers, including resistive 'liner' or barrier layers, to ensure proper function and prevent material interdiffusion. These liners, while serving a purpose, add parasitic electrical resistance, which slows down the chip's performance and increases its power consumption. They also make the manufacturing process more complex, increasing the risk of defects and reducing yield.\n\nThis patent addresses these issues by eliminating the resistive liners and creating a direct, highly conductive silicide contact, thereby reducing resistance, simplifying manufacturing, and enabling further miniaturization. Keywords: contact resistance, semiconductor scaling, manufacturing complexity, parasitic resistance, MOL bottleneck.","question":"What problem does Fully Silicided Linerless Middle-of-line (mol) Contact solve?"},{"answer":"The patent US-9853151, titled Fully Silicided Linerless Middle-of-line (mol) Contact, lists inventors associated with its development. Unfortunately, the specific inventor names were not provided in the prompt data. However, such innovations typically emerge from teams of highly specialized engineers and material scientists working at leading semiconductor research institutions or major chip manufacturing companies.\n\nThese teams are dedicated to pushing the boundaries of silicon technology, constantly seeking ways to improve chip performance, reduce power consumption, and enable greater miniaturization. The development of the Fully Silicided Linerless Middle-of-line (mol) Contact would have involved extensive research in materials science, process engineering, and device physics to perfect the 'linerless' silicidation technique. Keywords: patent inventors, semiconductor research, material scientists, process engineering, device physics.","question":"Who invented Fully Silicided Linerless Middle-of-line (mol) Contact?"},{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact offers several significant benefits that are crucial for the advancement of modern electronics:\n\n1.  **Ultra-Low Contact Resistance:** By eliminating resistive liner layers and forming a direct, fully silicided contact, this technology drastically reduces electrical resistance. This means faster signal propagation and higher current flow, leading to faster and more responsive chips.\n2.  **Enhanced Device Scaling and Density:** The simplified, linerless structure allows for smaller contact dimensions. This enables higher transistor density on a chip, which is vital for continuing the trend of miniaturization and packing more computational power into smaller spaces.\n3.  **Improved Power Efficiency:** Lower electrical resistance directly translates to less energy wasted as heat. This results in more power-efficient chips, leading to extended battery life for portable devices and reduced energy consumption in data centers.\n4.  **Simplified Manufacturing Process:** Eliminating several complex deposition and etch steps associated with liner layers reduces overall process complexity. This can lead to higher manufacturing yields and lower production costs. Keywords: low resistance, device scaling, power efficiency, manufacturing yield, chip performance.","question":"What are the key benefits of Fully Silicided Linerless Middle-of-line (mol) Contact?"},{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact distinguishes itself from prior art primarily through its 'linerless' design and direct silicidation approach. In conventional semiconductor fabrication (prior art), 'middle-of-line' (MOL) contacts typically involved multiple layers. After forming an initial silicide on the transistor's source/drain, a separate diffusion barrier or 'liner' layer (e.g., TiN, TaN) was deposited, followed by the main contact metal.\n\nThe key difference in this invention is the elimination of that resistive liner layer. Prior art liners, while preventing metal diffusion, added parasitic resistance and increased process complexity. This patent instead directly fills the contact pattern with silicon material, deposits a metallic layer, and then performs a silicidation process to form a homogenous, highly conductive silicide contact without any intermediate resistive films. This direct, simplified approach significantly reduces contact resistance and enables more aggressive scaling than traditional multi-layered methods. Keywords: prior art, linerless design, direct silicidation, contact resistance, multi-layered contacts, semiconductor innovation.","question":"How is Fully Silicided Linerless Middle-of-line (mol) Contact different from prior art?"},{"answer":"The Fully Silicided Linerless Middle-of-line (mol) Contact has the potential to impact a vast array of industries that rely on advanced semiconductor technology. Given its ability to enable faster, smaller, and more power-efficient chips, its influence will be widespread:\n\n1.  **Consumer Electronics:** Smartphones, laptops, tablets, wearables, and smart home devices will benefit from enhanced performance, longer battery life, and more compact designs.\n2.  **High-Performance Computing (HPC) & Data Centers:** This technology will drive advancements in CPUs, GPUs, and specialized accelerators, critical for cloud computing, big data analytics, and scientific research, leading to faster processing and reduced energy consumption.\n3.  **Artificial Intelligence (AI) & Machine Learning:** More efficient chips are fundamental for AI model training and inference, accelerating developments in autonomous systems, natural language processing, and computer vision.\n4.  **Telecommunications:** 5G and future wireless communication infrastructure will require high-performance, low-power chips, which this invention helps to enable.\n5.  **Automotive:** Advanced driver-assistance systems (ADAS), infotainment, and autonomous vehicles demand increasingly powerful and reliable semiconductors. Keywords: consumer electronics, HPC, AI, 5G, automotive, semiconductor industry impact.","question":"What industries will Fully Silicided Linerless Middle-of-line (mol) Contact impact?"},{"answer":"The patent for the Fully Silicided Linerless Middle-of-line (mol) Contact, identified as US-9853151, was filed on **September 17, 2015**. This marks the initial date when the application detailing this innovative semiconductor fabrication method was submitted to the patent office.\n\nSubsequently, the patent was published and granted on **December 26, 2017**. The publication date signifies when the patent document became publicly available, while the grant date confirms the legal protection conferred upon the invention. This timeline indicates a relatively swift examination process, underscoring the potential novelty and significance of the technology within the semiconductor industry. Keywords: patent filing date, patent publication date, patent grant date, US-9853151, semiconductor patent timeline.","question":"When was Fully Silicided Linerless Middle-of-line (mol) Contact filed/granted?"},{"answer":"The commercial applications of the Fully Silicided Linerless Middle-of-line (mol) Contact are extensive, driven by its ability to enhance the fundamental performance and efficiency of microchips. Any product or system that relies on advanced semiconductors stands to benefit:\n\n1.  **Next-Generation Processors:** CPUs, GPUs, and specialized AI processors for servers, personal computers, and mobile devices will be faster, more powerful, and consume less energy. This directly translates to competitive advantages for chip designers like Intel, AMD, Apple, and Nvidia.\n2.  **High-Density Memory:** While primarily focused on logic, the principles of efficient contact formation can also contribute to denser and faster memory chips, impacting DRAM and NAND flash products.\n3.  **IoT Devices:** The reduced power consumption and smaller footprint enabled by this technology are ideal for battery-powered Internet of Things (IoT) devices, extending their operational life and enabling more complex edge processing.\n4.  **Advanced Sensors & RF Chips:** Improved contact performance can enhance the sensitivity and speed of various sensors and radio frequency (RF) components, crucial for 5G, radar, and medical devices.\n\nUltimately, this patent enables manufacturers to produce superior, more competitive chips that meet the escalating demands of the modern technological landscape. Keywords: commercial applications, next-gen processors, high-density memory, IoT devices, advanced sensors, semiconductor market.","question":"What are the commercial applications of Fully Silicided Linerless Middle-of-line (mol) Contact?"},{"answer":"Future developments for the Fully Silicided Linerless Middle-of-line (mol) Contact are likely to focus on its integration into increasingly advanced process nodes and its potential for novel applications. As semiconductor fabrication pushes towards 2nm and sub-2nm nodes, the importance of ultra-low resistance contacts will only grow.\n\nWe can expect continued research into optimizing the specific materials used for the silicon fill and metallic layers, exploring new alloys or deposition techniques to achieve even lower resistivity and enhanced thermal stability. There will also be efforts to adapt this 'linerless' silicidation method for emerging transistor architectures like Gate-All-Around (GAA) FETs, where contact formation in highly confined geometries is a major challenge.\n\nFurthermore, this technology could be foundational for future innovations in 3D chip stacking, where efficient vertical interconnects are paramount. Its inherent simplicity and performance benefits make it a strong candidate for ensuring the long-term scalability and power efficiency of future microchips, enabling advancements in quantum computing interfaces, neuromorphic hardware, and other cutting-edge computing paradigms. Keywords: future developments, advanced process nodes, GAA FETs, 3D chip stacking, quantum computing, neuromorphic hardware, material optimization, scalability.","question":"What are the future developments expected for Fully Silicided Linerless Middle-of-line (mol) Contact?"}],"topics":["Fully Silicided Linerless Middle-of-line (mol) Contact","semiconductor manufacturing","MOL contact","silicidation process","chip scaling","relentless","demand","increased"],"tech_cluster":null},"seo":{"title":"Fully Silicided Linerless Middle-of-line (mol) Contact - US-9853151","description":"Discover the Fully Silicided Linerless Middle-of-line (mol) Contact patent (US-9853151). This innovation lowers contact resistance for faster, smaller chips. Explore its impact on semiconductor manufacturing.","keywords":["Fully Silicided Linerless Middle-of-line (mol) Contact","semiconductor manufacturing","MOL contact","silicidation process","chip scaling","contact resistance","US-9853151","patentable.app","microchip innovation","advanced electronics","device fabrication","low power chips","high performance computing"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9853151","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9853151","citation_suggestion":"Patentable. \"Fully silicided linerless middle-of-line (MOL) contact\" (US-9853151). https://patentable.app/patents/US-9853151","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9853151","json":"https://patentable.app/api/llm-context/US-9853151","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:35:27.168Z"}