{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9854686","patent":{"patent_number":"US-9854686","title":"Preparation method of a thin power device","assignee":null,"inventors":[],"filing_date":"2015-03-13T00:00:00.000Z","publication_date":"2017-12-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures."},"analysis":{"summary":"The Preparation Method of a Thin Power Device patent (US 9854686) introduces an innovative technique for fabricating compact and efficient power devices. The core innovation involves embedding a semiconductor chip into a substrate with interconnected contact pads on both the front and back surfaces. This approach addresses the limitations of traditional power device fabrication methods, which often struggle with interconnectivity and thermal management challenges.\n\nThe problem being solved is the increasing demand for smaller, more efficient power devices in modern electronics. Existing solutions often result in bulky devices with poor interconnectivity and thermal performance. This patent offers a solution by directly embedding the semiconductor chip into the substrate, minimizing the overall device thickness and improving heat dissipation.\n\nThe key technical approach involves forming a substrate with a first set of contact pads on the front surface and a second set on the back surface. These pads are electrically connected via interconnecting structures within the substrate. A through-opening is created, aligning with a third contact pad on the back surface, where the semiconductor chip is embedded. This configuration allows for direct attachment of the chip's back metal layer to the third contact pad and electrical connection of the chip's front electrodes to the first set of contact pads.\n\nThe business value and applications of this technology are significant. The Preparation Method of a Thin Power Device enables the creation of smaller, more efficient, and more reliable power devices for use in smartphones, tablets, wearable devices, and other electronic gadgets. This technology offers a competitive advantage by improving device performance, reducing manufacturing costs, and enabling new product designs.\n\nThe market opportunity for this innovation is substantial, driven by the increasing demand for compact and high-performance electronics. The Preparation Method of a Thin Power Device has the potential to transform the power electronics industry by enabling the development of next-generation electronic devices.","layman_explanation":"The Preparation Method of a Thin Power Device addresses a critical challenge in the electronics industry: how to make power components smaller and more efficient without sacrificing performance. Current power devices often limit the size and capabilities of electronic gadgets.\n\nThis innovation works by embedding the semiconductor chip, which is the heart of the power device, directly into a substrate (a base material). Imagine building a house and instead of placing the foundation on top of the ground, you dig into the ground and bury the foundation inside. This embedding technique minimizes the overall thickness of the device. Additionally, the invention uses interconnected contact pads on both sides of the substrate to improve the flow of electricity and manage heat more effectively. This is like creating a superhighway for electricity within the device.\n\nThis matters because it allows manufacturers to create smaller, more powerful, and more reliable electronic devices. The market impact is significant, as it enables the development of next-generation smartphones, tablets, wearable devices, and other gadgets. The competitive advantage lies in the improved performance and reduced size of the power components.\n\nLooking ahead, this technology could lead to even smaller and more efficient electronic devices. Market adoption is expected to increase as manufacturers seek to create more compact and powerful gadgets. This innovation has the potential to attract significant investment and drive further advancements in the field of power electronics.","technical_analysis":"The Preparation Method of a Thin Power Device, as detailed in US Patent 9854686, outlines a specific process for creating thin power devices with enhanced interconnectivity and thermal management. The technical architecture centers around a substrate with strategically placed contact pads and a through-opening for semiconductor chip embedding.\n\nThe implementation involves several critical steps. First, a substrate is prepared with a first set of contact pads on the front surface and a second set on the back surface. These pads are electrically connected via interconnecting structures formed inside the substrate. A through-opening is then created, aligning with a third contact pad attached to the back surface. This third contact pad is not electrically connected to the first set of contact pads. Next, a semiconductor chip is embedded into the through-opening. The back metal layer of the chip is attached to the third contact pad, providing a thermal dissipation path. Finally, the electrodes on the front surface of the chip are electrically connected to the first set of contact pads via conductive structures.\n\nThe algorithm specifics are not explicitly detailed in the patent but involve precise control over the fabrication process. This includes the formation of the interconnecting structures, the alignment and bonding of the semiconductor chip, and the electrical connection of the chip's electrodes to the contact pads.\n\nThe integration patterns involve the seamless integration of the semiconductor chip into the substrate. This requires careful consideration of the materials used, the dimensions of the components, and the electrical characteristics of the interconnections.\n\nThe performance characteristics of the resulting device are expected to be superior to those of traditional power devices. The reduced thickness, improved interconnectivity, and enhanced thermal management contribute to enhanced performance, reliability, and energy efficiency.\n\nThe code-level implications are not directly applicable, as this patent describes a fabrication process rather than a software algorithm. However, the design and control of the fabrication equipment may involve software-based control systems.","business_analysis":"The Preparation Method of a Thin Power Device patent (US 9854686) presents a significant business opportunity in the power electronics market. The innovation addresses the growing demand for smaller, more efficient, and more reliable power devices in a wide range of electronic applications.\n\nThe market opportunity size is substantial, driven by the increasing demand for compact electronics. Smartphones, tablets, wearable devices, and other portable gadgets require efficient power management solutions. The Preparation Method of a Thin Power Device enables the creation of power devices that meet these requirements, opening up a significant market for this technology.\n\nThe competitive advantages of this technology include reduced device thickness, improved interconnectivity, enhanced thermal management, and increased reliability. These advantages translate into improved performance, reduced manufacturing costs, and increased customer satisfaction. This technology enables the creation of next-generation electronic devices with superior performance and features.\n\nThe revenue potential for this technology is significant. The Preparation Method of a Thin Power Device can be licensed to manufacturers of power devices, generating revenue through licensing fees. The technology can also be used to manufacture power devices directly, generating revenue through product sales.\n\nThe business models that can be applied to this technology include licensing, manufacturing, and service. Licensing involves licensing the technology to other companies. Manufacturing involves manufacturing power devices using this technology. Service involves providing technical support and consulting services to customers.\n\nThe strategic positioning of this technology involves targeting the high-growth market for compact electronics. This requires a focus on developing power devices that meet the specific needs of this market. This also requires a strong focus on marketing and sales to reach potential customers.\n\nThe ROI projections for this technology are attractive. The Preparation Method of a Thin Power Device has the potential to generate significant revenue and profits, resulting in a high return on investment. This makes this technology an attractive investment opportunity.","faqs":null,"topics":["thin power device","semiconductor chip","interconnect","power management","miniaturization","preparation","method","power"],"tech_cluster":null},"seo":{"title":"Preparation Method of a Thin Power Device - Patent US-9854686","description":"Discover the Preparation Method of a Thin Power Device (US-9854686) for compact, efficient power devices. Full patent analysis, claims, and technical details.","keywords":["thin power device","semiconductor chip","interconnect","power management","miniaturization","patent","patent US-9854686"]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9854686","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9854686","citation_suggestion":"Patentable. \"Preparation method of a thin power device\" (US-9854686). https://patentable.app/patents/US-9854686","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9854686","json":"https://patentable.app/api/llm-context/US-9854686","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T16:37:54.473Z"}