{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-RE050874-B2","patent":{"patent_number":"US-RE050874-B2","title":"Memory arrays","assignee":"Micron Technology, Inc.","inventors":["Unknown"],"filing_date":null,"publication_date":"2026-04-21T00:00:00.000Z","cpc_codes":[],"num_claims":null,"abstract":"A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory arrays","description":"A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions havin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-RE050874-B2","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-RE050874-B2","citation_suggestion":"Patentable. \"Memory arrays\" (US-RE050874-B2). https://patentable.app/patents/US-RE050874-B2","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-RE050874-B2","json":"https://patentable.app/api/llm-context/US-RE050874-B2","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T09:40:20.999Z"}