High Bandwidth Memory and Method for Manufacturing the Same

This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0118559 filed at the Korean Intellectual Property Office on Sep. 2, 2024, the entire contents of which are incorporated herein by reference.

The present disclosure relates to a high bandwidth memory and a method for manufacturing the same.

A semiconductor industry sector is pursuing miniaturization, weight lightening, and thinning of a semiconductor package mounted on an electronic device while simultaneously achieving higher speed, multi-function, and large capacity in response to a demand for miniaturization and weight lightening of the electronic device. Accordingly, a need for a packaging technology capable of storing more data and transmitting data at a faster speed is increasing, and a high bandwidth memory (HBM) formed by stacking a plurality of individual semiconductor chips using the packaging technology is being developed and used (and may be beneficial).

The high bandwidth memory (HBM) may be manufactured by forming a memory stack in which memory dies are stacked on a base die, and as the number of memory dies disposed on the base die increases, it may be possible to implement the high bandwidth memory (HBM) having high performance. However, if the number of memory dies within the memory stack is increased so that the memory stack has a height above a certain height, a problem in which a stack void may occur at an interface between the memory dies at an upper portion of the memory stack and warpage may occur in the memory stack or heat may accumulate inside the memory stack so that performance of the high bandwidth memory (HBM) may be deteriorated, may occur.

A glass core to which a hybrid bonding process may be applied may be interposed between memory stacks. The memory stack may have a structure in which memory dies are stacked.

The glass core to which the hybrid bonding process may be applied may be interposed between memory stack structures. The memory stack structure may have a unit structure in which the stacked memory dies are covered by a molding material.

A base die and the memory dies may include dummy through-silicon vias. The dummy through-silicon vias may be electrically separated, and may be thermally connected to a heat dissipation structure.

Some example embodiments of inventive concepts include a first semiconductor stack including a plurality of first semiconductor dies stacked in a vertical direction; a glass core on the first semiconductor stack; and a second semiconductor stack on the glass core, the second semiconductor stack including a plurality of second semiconductor dies stacked in the vertical direction.

Some example embodiments of inventive concepts include a base die; a first memory stack structure on the base die, wherein the first memory stack structure includes a first lower bonding structure, a plurality of first memory dies stacked in a vertical direction on the first lower bonding structure, a first molding material covering the plurality of first memory dies on the first lower bonding structure, and a first upper bonding structure on the first molding material and the plurality of first memory dies; a glass interposer on the first memory stack structure, wherein the glass interposer includes a core base and a plurality of through-glass vias within the core base; and a second memory stack structure on the glass interposer, wherein the second memory stack structure includes a second lower bonding structure, a plurality of second memory dies stacked in the vertical direction on the second lower bonding structure, and a second molding material covering the plurality of second memory dies on the second lower bonding structure.

Some example embodiments of inventive concepts include a base die; a plurality of memory stacks stacked in a vertical direction on the base die, wherein each memory stack of the plurality of memory stacks includes a plurality of memory dies stacked in the vertical direction; one or more glass cores alternating with the plurality of memory stacks on the base die; and a molding material covering the plurality of memory stacks and the one or more glass cores on the base die.

Memory stacks or memory stack structures may be bonded by a glass core. As a result, it may be possible to prevent (or reduce a likelihood of) generation of a stack void at an interface between memory dies disposed at a high level, and it may be possible to reduce warpage of the memory dies disposed at the high level.

A high bandwidth memory may be manufactured in a separate process, and may be manufactured using the memory stack structures and the glass core that have been verified for reliability. Accordingly, a manufacturing process of the high bandwidth memory may be simplified, and productivity of the high bandwidth memory may be improved.

A base die and the memory dies may include dummy through-silicon vias. As a result, heat generated inside each of the base die and the memory dies may be released to the outside through the dummy through-silicon vias so that a heat dissipation characteristic of the high bandwidth memory is improved.

Various example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings so that those skilled in the art could implement the example embodiments. The present disclosure may be modified in various ways, all without departing from the spirit or scope of the present inventive concepts.

In order to describe the present inventive concepts, parts or portions that are irrelevant to the description are omitted, and identical or similar constituent elements throughout the specification are denoted by the same reference numerals.

In the drawings, a size and a thickness of each element are arbitrarily illustrated for ease of description, and the present inventive concepts are not necessarily limited to those illustrated in the drawings.

Throughout the specification, when a part is “connected” to another part, it includes not only a case where the part is “directly connected” but also a case where the part is “indirectly connected” with another part in between. Unless explicitly stated to the contrary, the word “includes,” “comprise” and variations such as “comprises,” “including,” and “comprising” should be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

It should be understood that when an element such as a layer, a film, a region, or a plate is referred to as being “on” or “above” another element, it may be directly on the other element, or an intervening element may also be present. In contrast, when an element is referred to as being “directly on” another element, there is no intervening element present. Further, in the specification, the word “on” or “above” means disposed on or below a referenced part, and does not necessarily mean disposed on the upper side of the referenced part based on a gravitational direction.

Throughout the specification, the phrase “in a plan view” or “on a plane” may mean when an object portion is viewed from above, and the phrase “in a cross-sectional view” or “on a cross-section” may mean when a cross-section taken by vertically cutting an object portion is viewed from the side.

When the terms “approximately,” “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “approximately,” “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “approximately,” “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

It will be understood that elements and/or properties thereof may be recited herein as being “the same” or “equal” as other elements, and it will be further understood that elements and/or properties thereof recited herein as being “the same” as, or “equal” to other elements may be “the same” as, or “equal” to or “substantially the same” as or “substantially equal” to the other elements and/or properties thereof. Elements and/or properties thereof that are “substantially the same” as or “substantially equal” to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances (e.g., ±10%). Elements and/or properties thereof that are the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.

100 100 100 100 100 Hereinafter, high bandwidth memories (HBM) ()A,B,C, andD of example embodiments and a method for manufacturing the same are described with reference to the drawings.

1 FIG. 2 FIG. 3 FIG. 100 130 is a cross-sectional view showing the high bandwidth memoryA of some example embodiments.andare cross-sectional views showing a glass coresome example embodiments.

1 FIG. 100 108 109 110 120 120 120 120 140 100 100 Referring to, the high bandwidth memoryA may include external connection members, connection pads, a base die (or a base logic die), memory stack structures (or semiconductor stack structures) ()A,B, andT, and a molding material. The high bandwidth memoryA may be a three-dimensional (3D) stacked dynamic random-access memory (DRAM) having high performance. The high bandwidth memoryA may have memory channels through a memory stack manufactured by vertically stacking memory dies to simultaneously implement shorter latency and higher bandwidth compared with a conventional DRAM product, and may reduce a total area occupied by individual DRAMs on a substrate so that it may be advantageous for high bandwidth per area and may reduce power consumption.

108 109 108 109 108 108 Each of the external connection membersmay be disposed between each of the connection padsand an external device. Each of the external connection membersmay electrically connect each of the connection padsto the external device. In some example embodiments, the external connection membersmay include a micro-bump or a solder ball. In some example embodiments, the external connection membersmay include at least one of tin, silver, lead, nickel, copper, and an alloy thereof, but example embodiments are not limited thereto.

109 110 109 112 110 108 109 112 110 108 109 The connection padsmay be disposed below the base die. Each of the connection padsmay be disposed between each of wires within a frontside structureof the base dieand each of the external connection members. Each of the connection padsmay electrically connect each of the wires within the frontside structureof the base dieto each of the external connection members. In some example embodiments, the connection padsmay include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and an alloy thereof, but example embodiments are not limited thereto.

110 1 12 110 110 110 110 The base diemay be disposed between the memory dies (D) Dto Dand the external device. The base diemay be a buffer die. When data are exchanged between devices with different data processing speeds, processing units, and usage times, data loss may occur due to a difference in the data processing speeds, the processing units, and the usage times between the devices. To prevent (or reduce the likelihood of) the loss (or data loss), the base diemay be disposed between the memory dies D and the external device so that information when data are exchanged between the memory dies D and the external device may be temporarily stored (or may be stored) in the base die. In some example embodiments, when data are transmitted to or received from the memory dies D, the base diemay sequentially pass the data after arranging an order of the data.

110 111 112 113 The base diemay include a die base, the frontside structure, through-silicon vias, and a bonding structure BS.

111 108 111 111 112 111 109 112 111 The die basemay be disposed so that a frontside thereof faces the external connection members. The die basemay be a die formed from a wafer. In some example embodiments, the die basemay include silicon or another semiconductor material. The frontside structuremay be disposed between the die baseand the connection pads. The frontside structuremay include an active layer and a wiring layer. The active layer may be disposed on a frontside of the die base. The active layer may include an integrated circuit structure having integrated circuit regions. In some example embodiments, the integrated circuit structure may include at least one of an active device and a passive device. In some example embodiments, the integrated circuit structure may include a gate structure, a source region, and a drain region. In some example embodiments, the integrated circuit structure may include at least one of a transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer may be disposed on the active layer. The wiring layer may include signal wiring lines, electric power wiring lines, contact plugs, and an inter-metal dielectric (IMD).

113 111 113 112 115 113 112 115 113 The through-silicon viasmay be disposed within the die base. Each of the through-silicon viasmay be disposed between the active layer or the wiring layer of the frontside structureand each of bonding padsof the bonding structure BS. Each of the through-silicon viasmay electrically connect the active layer or the wiring layer of the frontside structureto each of the bonding padsof the bonding structure BS. In some example embodiments, the through-silicon viasmay include at least one of tungsten, aluminum, copper, and an alloy thereof, but example embodiments are not limited thereto.

111 114 115 The bonding structure BS may be disposed on a backside of the die base. The bonding structure BS may include a silicon insulating layerand the bonding pads.

114 126 120 114 115 114 114 2 The silicon insulating layermay be directly bonded to a lower silicon insulating layerL of the memory stack structures. The silicon insulating layermay surround and insulate the bonding pads. In some example embodiments, the silicon insulating layermay include silicon oxide. In some example embodiments, the silicon insulating layermay include SiO, but example embodiments are not limited thereto.

115 114 115 114 115 114 115 113 115 127 120 110 120 115 127 115 The bonding padsmay be disposed through the silicon insulating layer. Levels of bonding surfaces of the bonding padsmay be the same as a level of a bonding surface of the silicon insulating layer. Side surfaces of the bonding padsmay be surrounded by the silicon insulating layer. Each of the bonding padsmay be electrically connected to each of the through-silicon vias. The bonding padsmay be directly bonded to lower bonding padsL of the memory stack structures. An electrical connection may be made between the base dieand the memory stack structuresby direct bonding between the bonding padsand the lower bonding padsL. In some example embodiments, the bonding padsmay include copper or a conductive material capable of applying hybrid bonding.

120 110 120 110 100 120 120 120 100 120 120 1 129 120 2 129 120 3 129 1 FIG. The memory stack structuresmay be disposed on the base die. The memory stack structuresmay be sequentially stacked above the base die. In, the high bandwidth memoryincluding three memory stack structuresA,B, andT is disclosed, but the example embodiments are not limited thereto, and the high bandwidth memoryincluding more or fewer memory stack structuresmay be included within the scope of the present inventive concepts. The first memory stack structureA may include a lower bonding structure LBS, a memory stack (or a semiconductor stack) S, a molding material, and an upper bonding structure UBS. The second memory stack structureB may include a lower bonding structure LBS, a memory stack (or a semiconductor stack) S, a molding material, and an upper bonding structure UBS. The third memory stack structureT may include a lower bonding structure LBS, a memory stack (or a semiconductor stack) S, and a molding material.

120 126 127 The lower bonding structure LBS may be disposed at a lowermost portion of the memory stack structure. The lower bonding structure LBS may include the lower silicon insulating layerL and the lower bonding padsL.

126 114 110 131 126 127 126 114 110 131 126 126 2 The lower silicon insulating layerL may be directly bonded to the silicon insulating layerof the base dieor a core base. The lower silicon insulating layerL may surround and insulate the lower bonding padsL. In some example embodiments, the lower silicon insulating layerL may include a material capable of performing non-metal-non-metal hybrid bonding with the silicon insulating layerof the base dieor the core base. In some example embodiments, the lower silicon insulating layerL may include silicon oxide. In some example embodiments, the lower silicon insulating layerL may include SiO, but example embodiments are not limited thereto.

127 126 127 126 127 126 127 122 127 127 115 110 132 130 110 120 130 120 127 115 132 127 The lower bonding padsL may be disposed through the lower silicon insulating layerL. Levels of bonding surfaces of the lower bonding padsL may be the same as a level of a bonding surface of the lower silicon insulating layerL. Side surfaces of the lower bonding padsL may be surrounded by the lower silicon insulating layerL. Each of the lower bonding padsL may be electrically connected to each of wires within a frontside structureof the memory die D adjacent to each of the lower bonding padsL. The lower bonding padsL may be directly bonded to the bonding padsof the base dieor through-glass viasof the glass core. An electrical connection may be made between the base dieand the memory stack structureor between the glass coreand the memory stack structureby direct bonding between the lower bonding padsL and the bonding padsor the through-glass vias. In some example embodiments, the lower bonding padsL may include copper or a conductive material capable of applying hybrid bonding.

1 2 3 1 FIG. Memory stacks(S) S, S, and Smay be disposed on the lower bonding structure LBS. The memory stack S may include the memory dies D stacked in a vertical direction. In, the memory stack S including four memory dies D is disclosed, but the example embodiments are not limited thereto, and the memory stack S including more or fewer memory dies D may be included within the scope of the present inventive concepts.

121 122 123 1 5 9 4 8 12 100 123 The memory die (a semiconductor die or a core die) D may include a memory die base, the frontside structure, a frontside bonding structure FBS, through-silicon vias, and a backside bonding structure BBS. The memory dies D, D, and Dadjacent to the lower bonding structure LBS may not include the frontside bonding structure FBS. The memory dies Dand Dadjacent to the upper bonding structure UBS may not include the backside bonding structure BBS. The memory die Ddisposed at an uppermost portion of the high bandwidth memoryA may not include the through-silicon viasand the backside bonding structure BBS. In some example embodiments, the memory dies D may each include a DRAM, but example embodiments are not limited thereto.

121 108 121 121 The memory die basemay be disposed so that a frontside thereof faces the external connection members. The memory die basemay be a die formed from a wafer. In some example embodiments, the memory die basemay include silicon or another semiconductor material.

122 121 122 121 The frontside structuremay be disposed on a frontside of the memory die base. The frontside structuremay include an active layer and a wiring layer. The active layer may be disposed on the frontside of the memory die base. The active layer may include an integrated circuit structure having integrated circuit regions. In some example embodiments, the integrated circuit structure may include at least one of an active device and a passive device. In some example embodiments, the integrated circuit structure may include a gate structure, a source region, and a drain region. In some example embodiments, the integrated circuit structure may include at least one of a transistor, a diode, a capacitor, an inductor, and a resistor. The wiring layer may be disposed on the active layer. The wiring layer may include signal wiring lines, electric power wiring lines, contact plugs, and an inter-metal dielectric (IMD).

122 126 127 The frontside bonding structure FBS may be disposed on the frontside structure. The frontside bonding structure FBS may include a frontside silicon insulating layerand frontside bonding pads.

126 124 126 126 127 126 126 2 The frontside silicon insulating layermay be directly bonded to a backside silicon insulating layerof the memory die D adjacent to the frontside silicon insulating layer. The frontside silicon insulating layermay surround and insulate the frontside bonding pads. In some example embodiments, the frontside silicon insulating layermay include silicon oxide. In some example embodiments, the frontside silicon insulating layermay include SiO, but example embodiments are not limited thereto.

127 126 127 126 127 126 127 122 127 125 127 127 125 127 The frontside bonding padsmay be disposed through the frontside silicon insulating layer. Levels of bonding surfaces of the frontside bonding padsmay be the same as a level of a bonding surface of the frontside silicon insulating layer. Side surfaces of the frontside bonding padsmay be surrounded by the frontside silicon insulating layer. Each of the frontside bonding padsmay be electrically connected to each of the wires within the frontside structure. The frontside bonding padsmay be directly bonded to backside bonding padsof the memory die D adjacent to the frontside bonding pads. An electrical connection may be made between the memory dies D by direct bonding between the frontside bonding padsand the backside bonding pads. In some example embodiments, the frontside bonding padsmay include copper or a conductive material capable of applying hybrid bonding.

123 121 123 122 125 123 122 125 123 The through-silicon viasmay be disposed within the memory die base. Each of the through-silicon viasmay be disposed between the active layer or the wiring layer of the frontside structureand each of the backside bonding padsof the backside bonding structure BBS. Each of the through-silicon viasmay electrically connect the active layer or the wiring layer of the frontside structureto each of the backside bonding padsof the backside bonding structure BBS. In some example embodiments, the through-silicon viasmay include at least one of tungsten, aluminum, copper, and an alloy thereof, but example embodiments are not limited thereto.

121 124 125 The backside bonding structure BBS may be disposed on a backside of the memory die base. The backside bonding structure BBS may include the backside silicon insulating layerand the backside bonding pads.

124 126 124 124 125 124 124 2 The backside silicon insulating layermay be directly bonded to the frontside silicon insulating layerof the memory die D adjacent to the backside silicon insulating layer. The backside silicon insulating layermay surround and insulate the backside bonding pads. In some example embodiments, the backside silicon insulating layermay include silicon oxide. In some example embodiments, the backside silicon insulating layermay include SiO, but example embodiments are not limited thereto.

125 124 125 124 125 124 125 123 125 127 125 125 127 125 The backside bonding padsmay be disposed through the backside silicon insulating layer. Levels of bonding surfaces of the backside bonding padsmay be the same as a level of a bonding surface of the backside silicon insulating layer. Side surfaces of the backside bonding padsmay be surrounded by the backside silicon insulating layer. Each of the backside bonding padsmay be electrically connected to each of the through-silicon vias. The backside bonding padsmay be directly bonded to the frontside bonding padsof the memory die D adjacent to the backside bonding pads. An electrical connection may be made between the memory dies D by direct bonding between the backside bonding padsand the frontside bonding pads. In some example embodiments, the backside bonding padsmay include copper or a conductive material capable of applying hybrid bonding.

129 129 The molding materialmay be disposed on the lower bonding structure LBS, and may cover the memory stack S. The molding materialmay have the same level as a level of an upper surface of the memory stack S.

129 124 125 The upper bonding structure UBS may be disposed on the memory stack S and the molding material. The upper bonding structure UBS may include an upper silicon insulating layerU and upper bonding padsU.

124 131 124 125 124 131 124 124 2 The upper silicon insulating layerU may be directly bonded to the core base. The upper silicon insulating layerU may surround and insulate the upper bonding padsU. In some example embodiments, the upper silicon insulating layerU may include a material capable of performing non-metal-non-metal hybrid bonding with the core base. In some example embodiments, the upper silicon insulating layerU may include silicon oxide. In some example embodiments, the upper silicon insulating layerU may include SiO, but example embodiments are not limited thereto.

125 124 125 124 125 124 125 123 125 125 132 130 130 120 125 132 125 The upper bonding padsU may be disposed through the upper silicon insulating layerU. Levels of bonding surfaces of the upper bonding padsU may be the same as a level of a bonding surface of the upper silicon insulating layerU. Side surfaces of the upper bonding padsU may be surrounded by the upper silicon insulating layerU. Each of the upper bonding padsU may be electrically connected to each of the through-silicon viasof the memory die D adjacent to each of the upper bonding padsU. The upper bonding padsU may be directly bonded to the through-glass viasof the glass core. An electrical connection may be made between the glass coreand the memory stack structureby direct bonding between the upper bonding padsU and the through-glass vias. In some example embodiments, the upper bonding padsU may include copper or a conductive material capable of applying hybrid bonding.

1 FIG. 2 FIG. 130 120 110 130 120 130 131 132 Referring toand, glass cores (or glass interposers)may be stacked alternately with the memory stack structureson the base die. Each of the glass coresmay be disposed between the memory stack structuresadjacent to each other. The glass coremay include the core baseand the through-glass vias (or first through-glass vias).

131 124 120 131 126 120 131 132 131 131 131 131 2 A first surface of the core basemay be directly bonded to the upper silicon insulating layerU of the upper bonding structure UBS of the memory stack structure. A second surface of the core basemay be directly bonded to the lower silicon insulating layerL of the lower bonding structure LBS of the memory stack structure. The second surface may be an opposite surface of the first surface. The core basemay surround and insulate the through-glass vias. In some example embodiments, the core basemay include quartz. In some example embodiments, the core basemay include silicon oxide. In some example embodiments, the core basemay include SiO, but example embodiments are not limited thereto. In some example embodiments, the core basemay have a thickness T in a vertical direction ranging from about 1 μm to about 100 μm, but example embodiments are not limited thereto.

132 131 132 125 125 120 132 127 127 120 120 132 131 132 131 132 131 132 132 132 The through-glass viasmay be disposed through the core base. Each first end (or each first bonding surface) of the through-glass viasmay be directly bonded to a corresponding the upper bonding padU among the upper bonding padsU of the upper bonding structure UBS of the memory stack structure. Each second end (or each second bonding surface) of the through-glass viasmay be directly bonded to a corresponding the lower bonding padL among the lower bonding padsL of the lower bonding structure LBS of the memory stack structure. The second end may be a portion opposite to the first end. An electrical connection may be made between the memory stack structuresby the direct bonding. A level of each first end (or each first bonding surface) of the through-glass viasmay be the same as a level of the first surface of the core base. A level of each second end (or each second bonding surface) of the through-glass viasmay be the same as a level of the second surface of the core base. Side surfaces of the through-glass viasmay be surrounded by the core base. In some example embodiments, the through-glass viasmay include copper or a conductive material capable of applying hybrid bonding. In some example embodiments, each of the through-glass viasmay have a width W in a horizontal direction ranging from about 0.01 μm to about 30 μm, but example embodiments are not limited thereto. In some example embodiments, adjacent through-glass viasmay be disposed with an interval P in a horizontal direction ranging from about 1 μm to about 30 μm, but example embodiments are not limited thereto.

132 131 132 131 Like a silicon material, a glass material may be formed so that a surface roughness thereof is about 10 nm or less, but example embodiments are not limited thereto. Accordingly, it may be possible to form the through-glass viashaving an ultra-fine pitch within the core baseof the glass material, and an interconnection structure capable of performing hybrid bonding may be formed based on the through-glass viasincluding copper and the core baseincluding silicon oxide.

131 A Young's modulus of the glass material may be about 50 to about 90 GPa, but example embodiments are not limited thereto. A Young's modulus of the silicon material may be about 165 GPa, but example embodiments are not limited thereto. Additionally or alternatively, a coefficient of thermal expansion (CTE) of the glass material may be about 3 to about 9 ppm/K, but example embodiments are not limited thereto. The coefficient of thermal expansion (CTE) of the silicon material may be about 2.9 to about 4 ppm/K, but example embodiments are not limited thereto. Because the glass material is more flexible than the silicon material and the core basemade of the glass material has a similar coefficient of thermal expansion to that of silicon that is a main material of the memory die D, a warpage characteristic that may occur due to a difference in coefficient of thermal expansion between the materials may be improved.

131 The glass material may have excellent flatness (or the glass material may have a flat surface and/shape). Therefore, if the core basemade of the glass material is used, a phenomenon of dishing and erosion occurring in a chemical mechanical polishing (CMP) process performed in a previous step of a hybrid bonding process may be adjusted. Thus, it may be possible to solve a problem of poor connection between bonding pads.

3 FIG. 130 133 131 130 134 131 Referring to, the glass coremay include a first silicon insulating layeron the first surface of the core base. The glass coremay include a second silicon insulating layeron the second surface of the core base.

133 124 120 134 126 120 131 133 134 132 133 134 133 134 133 134 126 124 126 124 133 134 126 124 126 124 131 1 133 2 134 3 2 2 The first silicon insulating layermay be directly bonded to the upper silicon insulating layerU of the upper bonding structure UBS of the memory stack structure. The second silicon insulating layermay be directly bonded to the lower silicon insulating layerL of the lower bonding structure LBS of the memory stack structure. The core base, the first silicon insulating layer, and the second silicon insulating layermay surround and insulate the through-glass vias. In some example embodiments, the first silicon insulating layerand the second silicon insulating layermay each include silicon nitride. In some example embodiments, each of the first silicon insulating layerand the second silicon insulating layermay include SiN or SiCN, but example embodiments are not limited thereto. In an example embodiment where the first silicon insulating layerand the second silicon insulating layerinclude SiN, the lower silicon insulating layerL, the upper silicon insulating layerU, the frontside silicon insulating layer, and the backside silicon insulating layermay each include SiN other than SiO, but example embodiments are not limited thereto. In an example embodiment where the first silicon insulating layerand the second silicon insulating layerinclude SiCN, the lower silicon insulating layerL, the upper silicon insulating layerU, the frontside silicon insulating layer, and the backside silicon insulating layermay each include SiCN other than SiO, but example embodiments are not limited thereto. In some example embodiments, the core basemay have a thickness Tin a vertical direction ranging from about 1 μm to about 100 μm, but example embodiments are not limited thereto. In some example embodiments, the first silicon insulating layermay have a thickness Tin the vertical direction ranging from about 0.05 μm to about 1 μm, but example embodiments are not limited thereto. In some example embodiments, the second silicon insulating layermay have a thickness Tin the vertical direction ranging from about 0.05 μm to about 1 μm, but example embodiments are not limited thereto.

132 131 133 134 132 133 132 134 132 131 133 134 The through-glass viasmay be disposed through the core base, the first silicon insulating layer, and the second silicon insulating layer. The level of each first end (or each first bonding surface) of the through-glass viasmay be the same as a level of a bonding surface of the first silicon insulating layer. The level of each second end (or each second bonding surface) of the through-glass viasmay be the same as a level of a bonding surface of the second silicon insulating layer. The side surfaces of the through-glass viasmay be surrounded by the core base, the first silicon insulating layer, and the second silicon insulating layer.

130 130 2 FIG. 3 FIG. The contents described with respect to the glass coreofmay be applied to the contents other than those described with respect to the glass coreof.

1 FIG. 140 110 120 130 140 120 Referring back to, the molding materialmay be disposed on the base die, and may cover the memory stack structuresand the glass cores. The molding materialmay have the same level as a level of an upper surface of the third memory stack structureT.

4 FIG. 100 is a cross-sectional view showing the high bandwidth memoryB according to some example embodiments.

4 FIG. 120 120 3 129 150 Referring to, a third memory stack structureT disposed at an uppermost portion of memory stack structuresmay include a lower bonding structure LBS, a memory stack (or a semiconductor stack) S, a molding material, and a heat dissipation structure.

150 129 3 150 150 150 The heat dissipation structuremay be disposed on the molding materialand the memory stack S. In some example embodiments, the heat dissipation structuremay include a heat slug, a heat sink, or a heat spreader, but example embodiments are not limited thereto. In some example embodiments, the heat dissipation structuremay include a conductive material having high thermal conductivity such as silicon, copper or aluminum, but example embodiments are not limited thereto. In some example embodiments, the heat dissipation structuremay include a thermal interface material (TIM). In some example embodiments, the thermal interface material (TIM) may include a thermal paste, a thermal pad, a phase change material (PCM), or a metal material, but example embodiments are not limited thereto. In some example embodiments, the thermal interface material (TIM) may include grease.

110 120 130 150 110 113 111 115 120 127 120 125 123 127 125 130 132 A base die, the memory stack structures, and glass coresmay include dummy structures H thermally connected to the heat dissipation structure(components in which H is added after a reference numeral of the drawings). The base diemay include dummy through-silicon viasH within a die baseand dummy bonding padsH of a bonding structure BS. The lower bonding structure LBS of each of the memory stack structuresmay include lower dummy bonding padsLH. The upper bonding structure UBS of each of the memory stack structuresmay include upper dummy bonding padsUH. Each of memory dies D may include dummy through-silicon viasH, dummy frontside bonding padsH of a frontside bonding structure FBS, and dummy backside bonding padsH of a backside bonding structure BBS. Each of the glass coresmay include dummy through-glass vias (or second through-glass vias)H.

150 110 130 110 150 150 100 The dummy structures H may be electrically separated, and may be thermally connected to the heat dissipation structure. The dummy structures H may be disposed at edges of the base die, the memory dies D, and the glass coreson a plane. The dummy structures H corresponding to each other may be connected in a line in a vertical direction. Heat generated from the base dieand the memory dies D may be transferred to the heat dissipation structurethrough the dummy structures H, and may be released to the outside through the heat dissipation structure. Accordingly, a heat dissipation characteristic of the high bandwidth memoryB may be improved.

100 100 1 FIG. 4 FIG. The contents described with respect to the high bandwidth memoryA ofmay be applied to the contents other than those described with respect to the high bandwidth memoryB of.

5 FIG. 100 is a cross-sectional view showing the high bandwidth memoryC of some example embodiments.

5 FIG. 131 130 129 120 140 120 130 131 Referring to, each of side surfaces of a core baseof a glass coremay be recessed (R) based on a corresponding side surface of the side surfaces of molding materialof memory stack structures, a corresponding side surface of side surfaces of a lower bonding structure LBS, and a corresponding side surface of side surfaces of an upper bonding structure UBS. A molding materialcovering the memory stack structuresand glass coresmay extend to contact the recessed side surfaces of the core base.

131 120 140 140 131 120 129 140 140 131 120 According to the present inventive concepts, the recessed side surfaces of the core bases, a portion of a lower surface, and a portion of an upper surface of the memory stack structuresmay be covered by the molding material. Accordingly, it may be possible to improve an adhesive force of the molding materialto the core basesand the memory stack structures. Additionally or alternatively, a progress of delamination or a crack that may occur along an interface between the molding materialand the molding materialmay be prevented (or reduced) by the molding materialextending to contact the side surfaces of the core base, so that damage to the memory stack structuresmay be prevented (or reduced).

100 100 4 FIG. 5 FIG. The contents described with respect to the high bandwidth memoryB ofmay be applied to the contents other than those described with respect to the high bandwidth memoryC of.

6 FIG. 100 is a cross-sectional view showing the high bandwidth memoryD of some example embodiments.

6 FIG. 100 110 1 2 3 130 140 110 130 110 1 1 4 2 5 8 3 9 12 140 130 110 Referring to, the high bandwidth memoryD may include a base die, memory stacks(S) S, S, and S, glass cores, and a molding material. The memory stacks S may be stacked in a vertical direction on the base die. The glass coresmay be stacked alternately with the memory stacks S on the base die. The memory stack Smay include memory dies Dto Dstacked in the vertical direction. The memory stack Smay include memory dies Dto Dstacked in the vertical direction. The memory stack Smay include memory dies Dto Dstacked in the vertical direction. The molding materialmay cover the memory stacks S and the glass coreson the base die.

The memory die D may include a frontside bonding structure FBS and a backside bonding structure BBS.

122 126 127 126 114 110 124 126 131 130 126 127 115 110 125 127 132 130 The frontside bonding structure FBS may be disposed on a frontside structure. The frontside bonding structure FBS may include a frontside silicon insulating layerand frontside bonding pads. The frontside silicon insulating layermay be directly bonded to a silicon insulating layerof the base die, a backside silicon insulating layerof the memory die D adjacent to the frontside silicon insulating layer, or a core baseof the glass coreadjacent to the frontside silicon insulating layer. The frontside bonding padsmay be directly bonded to bonding padsof the base die, backside bonding padsof the memory die D adjacent to the frontside bonding pads, or through-glass viasof the glass core.

121 124 125 124 126 124 131 130 124 125 127 125 132 130 125 The backside bonding structure BBS may be disposed on a backside of a memory die base. The backside bonding structure BBS may include the backside silicon insulating layerand the backside bonding pads. The backside silicon insulating layermay be directly bonded to the frontside silicon insulating layerof the memory die D adjacent to the backside silicon insulating layeror the core baseof the glass coreadjacent to the backside silicon insulating layer. The backside bonding padsmay be directly bonded to the frontside bonding padsof the memory die D adjacent to the backside bonding padsor the through-glass viasof the glass coreadjacent to the backside bonding pads.

130 131 132 131 124 131 131 126 131 The glass coremay include the core baseand the through-glass vias. A first surface of the core basemay be directly bonded to the backside silicon insulating layerof the memory die D adjacent to the first surface of the core base. A second surface of the core basemay be directly bonded to the frontside silicon insulating layerof the memory die D adjacent to the second surface of the core base. The second surface may be an opposite surface of the first surface.

132 131 132 125 125 132 127 127 The through-glass viasmay be disposed through (or disposed penetrating) the core base. A first end (or a first bonding surface) of each of the through-glass viasmay be directly bonded to a corresponding the backside bonding padamong the backside bonding padsof the memory die D adjacent to each first end. A second end (or A second bonding surface) of each of the through-glass viasmay be directly bonded to a corresponding frontside bonding padamong the frontside bonding padsof the memory die D adjacent to each second end. The second section may be a portion opposite to the first end.

100 100 4 FIG. 6 FIG. The contents described with respect to the high bandwidth memoryB ofmay be applied to the contents other than those described with respect to the high bandwidth memoryD of.

7 FIG. 8 FIG. 9 FIG. 10 FIG. 100 8 100 12 100 16 100 24 is a cross-sectional view showing a high bandwidth memory(S) including eight layers of memory dies D.is a cross-sectional view showing a high bandwidth memory(S) including 12 layers of memory dies D.is a cross-sectional view showing a high bandwidth memory(S) including 16 layers of memory dies D.is a cross-sectional view showing a high bandwidth memory(S) including 24 layers of memory dies D.

7 10 FIGS.to 120 120 120 Referring to, memory stack structuresmay include the same number of memory dies D, or may include different numbers of memory dies D. If the stacked memory dies have a height greater than or equal to a predetermined (or desired) height, a stack void may occur at an interface between the memory dies disposed at a high level. The number of the memory dies D included in a memory stack structuremay be designed in consideration of a height at which the memory dies may be stacked without occurrence of the stack void and efficiency of a manufacturing process of the memory stack structure.

7 FIG. 8 FIG. 100 8 120 1 4 120 5 8 100 12 120 1 4 120 5 8 120 9 12 100 12 120 1 6 120 7 12 100 12 120 1 8 120 9 12 Referring to, the high bandwidth memory(S) of some example embodiments may include a first memory stack structureA including four memory dies Dto Dand a second memory stack structureB including four memory dies Dto D. Referring to, the high bandwidth memory(S) of an example embodiment A may include a first memory stack structureA including four memory dies Dto D, a second memory stack structureB including four memory dies Dto D, and a third memory stack structureC including four memory dies Dto D. The high bandwidth memory(S) of an example embodiment B may include a first memory stack structureA including six memory dies Dto Dand a second memory stack structureB including six memory dies Dto D. The high bandwidth memory(S) of an example embodiment C may include a first memory stack structureA including eight memory dies Dto Dand a second memory stack structureB including four memory dies Dto D.

9 FIG. 100 16 120 1 4 120 5 8 120 9 12 120 13 16 100 16 120 1 8 120 9 16 100 16 120 1 8 120 9 12 120 13 16 Referring to, the high bandwidth memory(S) of an example embodiment A may include a first memory stack structureA including four memory dies Dto D, a second memory stack structureB including four memory dies Dto D, a third memory stack structureC including four memory dies Dto D, and a fourth memory stack structureD including four memory dies Dto D. The high bandwidth memory(S) of an example embodiment B may include a first memory stack structureA including eight memory dies Dto Dand a second memory stack structureB including eight memory dies Dto D. A high bandwidth memory(S) of an example embodiment C may include a first memory stack structureA including eight memory dies Dto D, a second memory stack structureB including four memory dies Dto D, and a third memory stack structureC including four memory dies Dto D.

10 FIG. 100 24 120 1 4 120 5 8 120 9 12 120 13 16 120 17 20 120 21 24 100 24 120 1 8 120 9 16 120 17 24 100 24 120 1 6 120 7 12 120 13 18 120 19 24 100 24 120 1 8 120 9 16 120 17 20 120 21 24 Referring to, the high bandwidth memory(S) of an example embodiment A may include a first memory stack structureA including four memory dies Dto D, a second memory stack structureB including four memory dies Dto D, a third memory stack structureC including four memory dies Dto D, a fourth memory stack structureD including four memory dies Dto D, a fifth memory stack structureE including four memory dies Dto D, and a sixth memory stack structureF including four memory dies Dto D. The high bandwidth memory(S) of an example embodiment B may include a first memory stack structureA including eight memory dies Dto D, a second memory stack structureB including eight memory dies Dto D, and a third memory stack structureC including eight memory dies Dto D. The high bandwidth memory(S) of an example embodiment C may include a first memory stack structureA including six memory dies Dto D, a second memory stack structureB including six memory dies Dto D, a third memory stack structureC including six memory dies Dto D, and a fourth memory stack structureD including six memory dies Dto D. The high bandwidth memory(S) of an example embodiment (D) may include a first memory stack structureA including eight memory dies Dto D, a second memory stack structureB including eight memory dies Dto D, a third memory stack structureC including four memory dies Dto D, and a fourth memory stack structureD including four memory dies Dto D.

120 120 The number of the memory dies D included in each memory stack structureis not limited to the above-described example embodiments, and the memory stack structureincluding various numbers of memory dies D may be included within the scope of the present inventive concepts.

11 19 FIGS.to 4 FIG. 5 FIG. 11 19 FIGS.to 1 FIG. 120 120 120 are cross-sectional views for describing a method for manufacturing the memory stack structuresofand. The method for manufacturing the memory stack structuresofmay be applied to a method for manufacturing the memory stack structureof.

11 FIG. 1 1 is the cross-sectional view showing a step of attaching the first memory die Don a first carrier C.

11 FIG. 1 1 1 Referring to, the first memory die Dmay be attached on the first carrier C. In some example embodiments, the first carrier Cmay include a silicon-based material such as glass or silicon oxide, another material such as an organic material or aluminum oxide, any combination thereof, or the like, but example embodiments are not limited thereto.

12 FIG. 2 3 4 1 is the cross-sectional view showing a step of sequentially stacking the second memory die D, the third memory die D, and the fourth memory die Don the first memory die D.

12 FIG. 2 1 124 1 126 2 124 126 1 2 124 1 126 2 Referring to, the hybrid bonding process may be performed to bond the second memory die Don the first memory die D. The chemical mechanical polishing (CMP) process may be performed before the hybrid bonding. In some example embodiments, a surface roughness of each of the bonding surfaces on which the hybrid bonding is performed may be about 10 Å or less. Next, the bonding surface of the backside silicon insulating layeron the first memory die Dand the bonding surface of the frontside silicon insulating layeron the second memory die Dmay be activated. In some example embodiments, the bonding surface of the backside silicon insulating layerand the bonding surface of the frontside silicon insulating layermay be surface treated by plasma activation. Next, the first memory die Dand the second memory die Dmay be aligned for the hybrid bonding. Next, the activated bonding surface of the backside silicon insulating layeron the first memory die Dmay contact the activated bonding surface of the frontside silicon insulating layeron the second memory die Dto perform pre-bonding.

1 2 124 1 126 2 124 1 126 2 Thereafter, the first memory die Dand the second memory die Dmay be hybrid bonded. First, the backside silicon insulating layeron the first memory die Dand the frontside silicon insulating layeron the second memory die Dmay be bonded by treatment. The treatment may strengthen bonding of the pre-bonded backside silicon insulating layeron the first memory die Dto the pre-bonded frontside silicon insulating layeron the second memory die D.

125 1 127 2 Next, each of the backside bonding padson the first memory die Dand each of the frontside bonding padson the second memory die Dmay be bonded by annealing.

3 2 4 3 Thereafter, the same hybrid process may be performed to bond the third memory die Don the second memory die Dand bond the fourth memory die Don the third memory die D.

13 FIG. 1 2 3 4 1 is the cross-sectional view showing a step of molding the first memory die D, the second memory die D, the third memory die D, and the fourth memory die Don the first carrier C.

13 FIG. 1 2 3 4 129 1 1 2 3 4 129 129 Referring to, the first memory die D, the second memory die D, the third memory die D, and the fourth memory die Dmay be covered with the molding materialon the first carrier C. In some example embodiments, the process of molding the first memory die D, the second memory die D, the third memory die D, and the fourth memory die Dwith the molding materialmay include a compression molding or transfer molding process. In some example embodiments, the molding materialmay include an epoxy molding compound (EMC), but example embodiments are not limited thereto.

14 FIG. 129 is the cross-sectional view showing a step of performing a chemical mechanical polishing (CMP) process on the molding material.

14 FIG. 129 4 Referring to, an upper surface of the molding materialmay be planarized by performing the chemical mechanical polishing (CMP) process. After the chemical mechanical polishing (CMP) process is performed, an upper surface of the fourth memory die Dmay be exposed.

15 FIG. 129 4 is the cross-sectional view showing a step of forming the upper bonding structure UBS on the molding materialand the fourth memory die D.

15 FIG. 124 129 4 125 125 Referring to, the upper silicon insulating layerU may be formed on the molding materialand on the fourth memory die D. Thereafter, a photolithography process and an etching process may be performed to form openings in which the upper bonding padsU are to be formed, and after a seed metal layer is applied, an electrolytic plating process may be performed so that the openings are filled to form the upper bonding padsU.

16 FIG. 1 is the cross-sectional view showing a step of removing the first carrier C.

16 FIG. 1 1 129 Referring to, the first carrier Cmay be removed from the first memory die Dand the molding material.

17 FIG. 2 is the cross-sectional view showing a step of attaching a second carrier C.

17 FIG. 2 Referring to, the second carrier Cmay be attached on the upper bonding structure UBS.

18 FIG. 129 1 is the cross-sectional view showing a step of forming the lower bonding structure LBS on the molding materialand the first memory die D.

18 FIG. 126 129 1 127 127 Referring to, the lower silicon insulating layerL may be deposited on the molding materialand the first memory die D. Thereafter, a photolithography process and an etching process may be performed to form openings in which the lower bonding padsL are to be formed, and after a seed metal layer is applied, an electrolytic plating process may be performed so that the openings are filled to form the lower bonding padsL.

19 FIG. 2 is the cross-sectional view showing a step of removing the second carrier C.

19 FIG. 2 Referring to, the second carrier Cmay be removed from the upper bonding structure UBS.

20 23 FIGS.to 5 FIG. 100 are cross-sectional views showing a method for manufacturing the high bandwidth memoryC of.

20 FIG. 120 110 is the cross-sectional view showing a step of stacking the first memory stack structureA on the base die.

20 FIG. 12 FIG. 120 110 Referring to, a hybrid bonding process may be performed to bond the first memory stack structureA on the base die. The hybrid bonding process may be applied to the contents of the hybrid bonding process described with reference to.

21 FIG. 130 120 is the cross-sectional view showing a step of stacking the glass coreon the first memory stack structureA.

21 FIG. 130 120 Referring to, a hybrid bonding process may be performed to bond the glass coreon the first memory stack structureA.

22 FIG. 120 130 120 130 is the cross-sectional view showing a step of stacking the second memory stack structureB, the glass core, and the third memory stack structureT on the glass core.

22 FIG. 120 130 120 130 Referring to, the second memory stack structureB, the glass core, and the third memory stack structureT may be sequentially bonded on the glass coreby performing a hybrid bonding process.

23 FIG. 130 120 120 120 110 is the cross-sectional view showing a step of molding the glass cores, the first memory stack structureA, the second memory stack structureB, and the third memory stack structureT on the base die.

23 FIG. 5 FIG. 130 120 120 120 140 110 130 120 120 120 140 140 150 100 150 Referring to, the glass cores, the first memory stack structureA, the second memory stack structureB, and the third memory stack structureT may be covered with the molding materialon the base die. In some example embodiments, the process of molding the glass cores, the first memory stack structureA, the second memory stack structureB, and the third memory stack structureT may include a compression molding or transfer molding process. In some example embodiments, the molding materialmay include an epoxy molding compound (EMC). Thereafter, an upper surface of the molding materialmay be planarized by performing a chemical mechanical polishing (CMP) process. After the chemical mechanical polishing (CMP) process is performed, an upper surface of the heat dissipation structuremay be exposed. Like the high bandwidth memoryC shown in, the upper surface of the heat dissipation structuremay be exposed after the chemical mechanical planarization (CMP) process is performed.

24 FIG. 31 FIG. 6 FIG. 100 toare cross-sectional views showing a method for manufacturing the high bandwidth memoryD of.

24 FIG. 1 110 is the cross-sectional view showing a step of stacking the first memory die Don the base die.

24 FIG. 12 FIG. 1 110 Referring to, the first memory die Dmay be bonded on the base dieby performing a hybrid bonding process. The hybrid bonding process may be applied to the contents of the hybrid bonding process described with reference to.

25 FIG. 2 3 4 1 is the cross-sectional view showing a step of sequentially stacking the second memory die D, the third memory die D, and the fourth memory die Don the first memory die D.

25 FIG. 2 3 4 1 Referring to, the second memory die D, the third memory die D, and the fourth memory die Dmay be sequentially bonded on the first memory die Dby performing a hybrid bonding process.

26 FIG. 130 4 is the cross-sectional view showing a step of stacking the glass coreon the fourth memory die D.

26 FIG. 130 4 Referring to, a hybrid bonding process may be performed to bond the glass coreon the fourth memory die D.

27 FIG. 5 6 7 8 130 is the cross-sectional view showing a step of sequentially stacking the fifth memory die D, the sixth memory die D, the seventh memory die D, and the eighth memory die Don the glass core.

27 FIG. 5 6 7 8 130 Referring to, the fifth memory die D, the sixth memory die D, the seventh memory die D, and the eighth memory die Dmay be sequentially bonded on the glass coreby performing a hybrid bonding process.

28 FIG. 130 8 is the cross-sectional view showing a step of stacking the glass coreon the eighth memory die D.

28 FIG. 130 8 Referring to, a hybrid bonding process may be performed to bond the glass coreon the eighth memory die D.

29 FIG. 9 10 11 12 130 is the cross-sectional view showing a step of sequentially stacking the ninth memory die D, the tenth memory die D, the eleventh memory die D, and the twelfth memory die Don the glass core.

29 FIG. 9 10 11 12 130 Referring to, a hybrid bonding process may be performed to sequentially bond the ninth memory die D, the tenth memory die D, the eleventh memory die D, and the twelfth memory die Don the glass core.

30 FIG. 150 12 is the cross-sectional view showing a step of attaching the heat dissipation structureon the twelfth memory die D.

30 FIG. 150 12 Referring to, the heat dissipation structuremay be attached on the twelfth memory die D.

31 FIG. 130 1 12 110 is the cross-sectional view showing a step of molding the glass coresand the first to twelfth memory dies Dto Don the base die.

31 FIG. 6 FIG. 130 1 12 140 110 130 1 12 140 140 100 150 Referring to, the glass coresand the first to twelfth memory dies Dto Dmay be covered with the molding materialon the base die. In some example embodiments, the process of molding the glass coresand the first to twelfth memory dies Dto Dmay include a compression molding or transfer molding process. In some example embodiments, the molding materialmay include an epoxy molding compound (EMC). Thereafter, an upper surface of the molding materialmay be planarized by performing a chemical mechanical polishing (CMP) process. Like the high bandwidth memoryD shown in, an upper surface of the heat dissipation structuremay be exposed after the chemical mechanical planarization (CMP) process is performed.

While this disclosure has been described in connection with some example embodiments, it should be understood that the disclosure is not limited to the disclosed example embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.