Semiconductor Package

This application claims priority to Korean Patent Application No. 10-2024-0172770, filed on Nov. 27, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

Embodiments of the present disclosure relate to a semiconductor package, and more particularly, to a semiconductor package including a photonic integrated circuit (PIC) chip.

With the development of the electronics industry, electronic components have increasingly been required to be relatively high functionalized and miniaturized and have high speed. With this trend, the need for miniaturization and multifunctionalization of semiconductor chips used in electronic parts has increased. In addition, in the field of semiconductor packages, the size is being reduced based on compact semiconductor chips. Furthermore, due to the demand for improved performance and reduced form factor of semiconductor packages, semiconductor package structures are moving toward multi-chip integrated structures. Multi-chip integration refers to integrating chips having different functions together into a single semiconductor package. Recently, PIC chips and electronic integrated circuit (EIC) chips have been integrated into a single semiconductor package.

One or more embodiments provide a semiconductor package including an electronic integrated circuit (EIC) chip and a photonic integrated circuit (PIC) chip in a structure, which is highly compatible with semiconductor package processes and facilitates transmission of optical signals, and a method of manufacturing the semiconductor package.

According to an aspect of one or more embodiments, there is provided a semiconductor package including a redistribution substrate, an electronic integrated circuit (EIC) chip on the redistribution substrate, an optical path bridge chip on the redistribution substrate, the optical path bridge chip on the EIC chip in a horizontal direction and including a first waveguide (WG) extending in the horizontal direction, a photonic integrated circuit (PIC) chip on the EIC chip and the optical path bridge chip, the PIC chip including a second WG extending in the horizontal direction, and a transparent support layer on the PIC chip, wherein a portion of the first WG overlaps a portion of the second WG in a vertical direction, and wherein the PIC chip is configured to provide an optical signal to be transmitted external to the semiconductor package through the second WG, the first WG, and the transparent support layer.

According to another aspect of one or more embodiments, there is provided a semiconductor package including a redistribution substrate, an electronic integrated circuit (EIC) chip on the redistribution substrate, the EIC chip including a through electrode, an optical path bridge chip on the redistribution substrate, the optical path bridge chip on the EIC chip in a horizontal direction and including a first waveguide (WG) extending in the horizontal direction, a photonic integrated circuit (PIC) chip on the EIC chip and the optical path bridge chip, the PIC chip including a second WG extending in the horizontal direction, a multi-insulating layer on the EIC chip, the optical path bridge chip, and the PIC chip, and a transparent support layer on the PIC chip and the multi-insulating layer, wherein a portion of the first WG overlaps a portion of the second WG in a vertical direction, wherein the PIC chip is configured to provide an optical signal to be transmitted external to the semiconductor package through the second WG, the first WG, the multi-insulating layer, and the transparent support layer, and wherein the through electrode is configured to transmit an electronic signal between the PIC chip and the EIC chip.

According to still another aspect of one or more embodiments, there is provided a semiconductor package including a base substrate, a first semiconductor device on the base substrate, a second semiconductor device on the base substrate and a left side of the first semiconductor device in a horizontal direction, and a first optical communication package on the base substrate and a right side of the first semiconductor device in the horizontal direction, the first optical communication package being configured to perform optical communication, wherein the first optical communication package includes a redistribution substrate, an electronic integrated circuit (EIC) chip on the redistribution substrate, an optical path bridge chip on the redistribution substrate, the optical path bridge chip on the EIC chip in the horizontal direction and including a first waveguide (WG) extending in the horizontal direction, a photonic integrated circuit (PIC) chip on the EIC chip and the optical path bridge chip, the PIC chip including a second WG extending in the horizontal direction, a multi-insulating layer on the EIC chip, the optical path bridge chip, and the PIC chip, and a transparent support layer on the PIC chip and the multi-insulating layer, wherein a portion of the first WG overlaps a portion of the second WG in a vertical direction, and wherein the PIC chip is configured to provide an optical signal to be transmitted to external to the semiconductor package through the second WG, the first WG, the multi-insulating layer, and the transparent support layer.

According to still another aspect of one or more embodiments, there is provided a method of manufacturing a semiconductor package, the method including forming a transparent support layer, forming a photonic integrated circuit (PIC) chip on the transparent support layer, the PIC chip including a first waveguide (WG) extending in a horizontal direction, forming an electronic integrated circuit (EIC) chip on the PIC chip, and forming an optical path bridge chip on the PIC chip and at a side of the EIC chip in the horizontal direction, the optical path bridge chip including a second WG extending in the horizontal direction, wherein a portion of the first WG overlaps a portion of the second WG in a vertical direction, and wherein the PIC chip is configured to provide an optical signal to be transmitted to an outside of the semiconductor package through the first WG, the second WG, and the transparent support layer.

The method may further include forming a reflector in the optical path bridge chip, the reflector being on the second WG in the horizontal direction and being configured to reflect the optical signal in the vertical direction to be incident to the transparent support layer.

The forming of the EIC chip may include forming a first body layer, an active layer on a first surface the first body layer, forming a lower pad on a second surface of the first body layer, forming an upper pad on a first surface of the active layer, forming a through electrode passing through the first body layer and connecting the lower pad to the active layer, and forming a chip pad in the PIC chip is connected to the upper pad.

The forming the chip pad may include forming the chip pad to be connected to the upper pad through one of hybrid copper bonding (HCB) and a connection terminal.

The forming of the PIC chip may include forming a second body layer, forming a buried oxide (BOX) layer on a surface of the second body layer, forming an optical passive device in the BOX layer, the second WG being in the BOX layer, and a chip pad on a surface of the BOX layer, and wherein the chip pad is on a portion of the bottom surface of the BOX layer overlapping the EIC chip in the vertical direction and connected to an upper pad of the EIC chip.

The method may further include forming a first insulating layer on transparent support layer and a side surface of the PIC chip, and forming a second insulating layer on the first insulating layer, the optical path bridge chip, and a side surface of the PIC chip, wherein the second insulating layer is transparent and is configured to provide an optical path from the optical path bridge chip to the transparent support layer.

The method may further include bonding the transparent support layer to the PIC chip via a bonding interface layer, wherein the transparent support layer may include an anti-reflective layer at a bottom of the transparent support layer.

The method may further include forming an optical coupler in the transparent support layer that is connected to an optical fiber, wherein the optical coupler is configured to transmit the optical signal to the optical fiber.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like reference characters denote like elements, and redundant descriptions thereof will be omitted.

It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and/or sections (collectively “elements”), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element described in this description section may be termed a second element or vice versa in the claim section without departing from the teachings of the disclosure.

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

As used herein, an expression “at least one of” preceding a list of elements modifies the entire list of the elements and does not modify the individual elements of the list. For example, an expression, “at least one of a, b, and c” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

1 FIG. 2 2 FIGS.A toC 1 FIG. is a cross-sectional view of a semiconductor package according to one or more embodiments.are a perspective view and plan views of a coupling structure of a first waveguide (WG) of an optical path bridge chip and a second WG of a photonic integrated circuit (PIC) chip in the semiconductor package of.

1 2 FIGS.toC 1000 Referring to, a semiconductor packageof one or more embodiments may correspond to a semiconductor package for co-packaged optics (CPO). CPO is heterogeneous integration technology that integrates an optical engine (or an optical module) and a switch semiconductor chip into a single package substrate. Recently, with the advent of the artificial intelligence (AI) era, much research and development has been conducted on CPO for an ultrahigh-speed, high-efficient data computing process.

1000 100 200 300 400 500 100 200 300 200 200 100 200 100 101 110 110 110 The semiconductor packageof one or more embodiments may include a redistribution substrate, an electronic integrated circuit (EIC) chip, an optical path bridge chip, a PIC chip, and a transparent support layer. The redistribution substratemay be arranged below the EIC chipand the optical path bridge chipand may redistribute a pad of the EIC chipto a region outside the EIC chip. For example, the redistribution substratemay correspond to a fan-out redistribution substrate used to expand the footprint of the EIC chip. For example, the redistribution substratemay include a redistribution body layerand a redistribution line. The redistribution linemay be formed in multiple layers. Redistribution linesin different layers may be connected to each other through a via.

101 101 101 110 101 101 101 1 FIG. The redistribution body layermay include an insulating material, e.g., photo-imageable dielectric (PID) resin, and may further include an inorganic filler. However, the material of the redistribution body layeris not limited to those mentioned above. The redistribution body layermay have a multi-layer structure according to a multi-layer structure of the redistribution line. However, for convenience, it is illustrated inthat the redistribution body layerhas a single-layer structure. When the redistribution body layerhas a multi-layer structure, the redistribution body layermay include only one material, or at least one layer may include a different material than the other layers.

150 101 150 101 150 110 100 A first external connection terminalmay be arranged on the bottom surface of the redistribution body layer. The first external connection terminalmay be arranged on a substrate pad on the bottom surface of the redistribution body layer. The first external connection terminalmay be electrically and/or physically connected to the redistribution lineof the redistribution substrate.

150 100 200 100 200 100 230 200 200 110 150 The first external connection terminalmay be arranged on a portion of the redistribution substrate, which corresponds to the bottom surface of the EIC chip, and a portion of the redistribution substrate, which extends in an x-direction and a y-direction on the bottom surface of the EIC chip. Consequently, the redistribution substratemay redistribute a first padof the EIC chipto a wider area than an area of the bottom surface of the EIC chipthrough the redistribution lineand the first external connection terminal.

150 152 154 150 154 152 152 152 152 100 For example, the first external connection terminalmay include a pillarand solder. However, embodiments are not limited thereto, and for example, the first external connection terminalmay include only the solder. For example, the pillarmay include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. In one or more embodiments, the pillarmay operation as a pad and include Cu. Accordingly, the pillarmay be referred to as a bump pad, a Cu pad, or a Cu pillar. When the pillaroperates as a pad, a separate pad may not be formed on the bottom surface of the redistribution substrate.

154 152 154 154 154 The soldermay be arranged on the pillar. The soldermay include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and/or an alloy thereof. For example, the soldermay include Sn, Sn—Ag, Sn—Au, Sn—Cu, Sn—Bi, Sn—Zn, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Ag—Zn, Sn—Cu—Bi, Sn—Cu—Zn, Sn—Bi—Zn, or the like. In some embodiments, the soldermay be referred to as a bump or a solder bump.

200 100 200 201 210 220 230 240 201 201 201 201 201 201 The EIC chipmay be mounted on the redistribution substrate. The EIC chipmay include a first body layer, an active layer, a through electrode, the first pad, and a protective layer. For example, the first body layermay include a semiconductor element, such as silicon (Si) or germanium (Ge). The first body layermay include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first body layermay have a silicon-on-insulator (SOI) structure. For example, the first body layermay include a buried oxide (BOX) layer. The first body layermay include a conductive region, e.g., an impurity-doped well or a structure such as an impurity-doped source/drain region. The first body layermay include various isolation structures including a shallow trench isolation (STI) structure.

210 The active layermay include an integrated circuit layer and a wiring layer on the integrated circuit layer. The integrated circuit layer may include various kinds of devices. For example, the integrated circuit layer may include various kinds of active devices and/or passive devices, such as a transistor, logic devices, memory devices, a system large scale integration (LSI), a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), and a micro-electro-mechanical system (MEMS).

1000 400 210 200 200 400 400 In the semiconductor packageaccording to one or more embodiments, various elements supporting the operation of the PIC chipmay be included in the integrated circuit layer of the active layerof the EIC chip. For example, the integrated circuit layer of the EIC chipmay include a trans-impedance amplifier (TIA), a clock and data recovery (CDR) circuit, and at least one driver. In one or more embodiments, the TIA may be a sort of current-to-voltage converter and may include at least one operational amplifier. The TIA may amplify the current output of a photodetector or other type of sensor of the PIC chipto a usable voltage. The TIA may provide low impedance to a photodiode of the PIC chip.

400 In one or more embodiments, the CDR circuit may extract timing information and data information from a serial data stream in the serial communication of digital data. In one or more embodiments, some relatively high-speed serial data streams may be transmitted without a clock signal. The CDR circuit may generate a clock signal from an appropriate frequency reference and then phase shift the clock signal to match the transition of a data stream. In one or more embodiments, the driver may be used to drive the various operations of the PIC chip.

201 220 220 230 230 200 1000 210 201 220 210 201 220 u The wiring layer may connect at least two devices to each other, connect devices to the conductive region of the first body layer, or connect devices to the through electrode. The wiring layer may also connect the through electrodeto the first pad, e.g., a first upper pad. For example, the wiring layer may include wires and a contact or a via. In the EIC chipof the semiconductor packageof one or more embodiments, the active layermay be arranged above the first body layerand the through electrode. However, embodiments are not limited thereto, and for example, the active layermay be arranged below the first body layerand the through electrode.

220 201 201 220 210 200 1000 201 220 The through electrodemay extend from the top to the bottom of the first body layerthrough the first body layer. In one or more embodiments, the through electrodemay extend into the active layer. In the EIC chipof the semiconductor packageof one or more embodiments, the first body layermay include Si, and accordingly, the through electrodemay correspond to a through-silicon via (TSV).

220 220 201 220 210 The through electrodemay have a pillar shape and include a barrier film on an outer surface thereof and a buried conductive layer therein. The barrier film may include at least one material selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boride (NiB). The buried conductive layer may include at least one material selected from the group consisting of copper (Cu), Cu alloys, such as copper tin (CuSn), copper magnesium (CuMg), copper nickel (CuNi), copper zinc (CuZn), copper palladium (CuPd), copper gold (CuAu), copper rhenium (CuRe), and copper tungsten (CuW), W, W alloys, Ni, Ru, and Co. An insulating layer may be between the through electrodeand the first body layeror between the through electrodeand the active layer. For example, the insulating layer may include an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof.

230 230 230 230 201 220 230 210 210 230 200 1000 230 230 u d d u The first padmay include the first upper padand a first lower pad. The first lower padmay be arranged on the bottom surface of the first body layerand connected to the through electrode. The first upper padmay be arranged on the top surface of the active layerand connected to the wiring layer of the active layer. For example, the first padmay include at least one selected from the group consisting of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In the EIC chipof the semiconductor packageof one or more embodiments, the first padmay include Cu. However, the material of the first padis not limited to Cu.

240 201 240 200 1000 240 240 200 300 600 610 240 240 200 The protective layermay be arranged on the bottom surface of the first body layer. For example, the protective layermay include an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. In the EIC chipof the semiconductor packageof one or more embodiments, the protective layermay have a single-layer or multi-layer structure. The protective layermay extend in a horizontal direction in the EIC chipand cover the bottom surface of the optical path bridge chipand the bottom surface of a multi-insulating layer, e.g., a first insulating layer. In one or more embodiments, due to this structure of the protective layer, the protective layermay be excluded from the elements of the EIC chip.

230 240 230 240 240 230 201 240 220 230 440 400 210 d d d u The first lower padmay pass through at least a portion of the protective layer. For example, the first lower padmay pass through at least a portion of the protective layerand may be buried in the protective layer. The first lower padmay be on the bottom surface of the first body layeror in the protective layerand connected to the through electrode. The first upper padmay be connected to a second padof the PIC chip. A protective layer may be arranged on the top surface of the active layer.

300 100 200 300 400 300 301 310 320 330 The optical path bridge chipmay be arranged on the redistribution substrateand adjacent to the EIC chip. The optical path bridge chipmay provide a path for transmission of an optical signal from or to the PIC chip. The optical path bridge chipmay include a second body layer, a first BOX layer, a first WG, and a reflector.

301 301 For example, the second body layermay include a semiconductor element, such as silicon (Si) or germanium (Ge). The second body layermay include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

310 301 310 310 320 310 320 320 320 320 310 320 2 2 The first BOX layermay be above the second body layer. For example, the first BOX layermay include silicon oxide (SiO). However, the material of the first BOX layeris not limited to SiO. The first WGmay be arranged inside the first BOX layer. The first WGmay extend in the x-direction. For example, the first WGmay include SiNx. However, the material of the first WGis not limited to SiNx. For example, the first WGmay include Si. The first BOX layermay correspond to a clad layer and the first WGmay correspond to a core layer.

330 320 330 320 320 1 330 330 330 1 FIG. The reflectormay be adjacent to an end of the first WGin the x-direction. As shown in, the reflectormay not be in contact with the first WGand may be spaced apart from the end of the first WGby a first distance Din the x-direction. The reflectormay change the traveling direction of an optical signal from the horizontal direction into the vertical direction. The reflectormay include an oblique metal plate. For example, the top surface of the metal plate of the reflectormay be inclined at 45 degrees with respect to an optical signal traveling in the horizontal direction.

400 400 200 300 200 400 300 400 200 400 1 FIG. As an integrated circuit chip using light, the PIC chiphas recently been developed at an accelerated pace for transmission of large-capacity information, ultrahigh-speed signal processing, minimization of transmission loss, and minimization of energy consumption. The PIC chipmay be arranged on the EIC chipand the optical path bridge chip. As shown in, in the vertical direction, e.g., the z-direction, the whole of the EIC chipmay overlap the PIC chip, and a portion of the optical path bridge chipmay overlap the PIC chip. However, embodiments are not limited thereto, and for example, only a portion of the EIC chipmay overlap the PIC chipin the z-direction.

400 401 410 420 430 401 401 The PIC chipmay include a third body layer, a second BOX layer, a second WG, and an optical passive device region. For example, the third body layermay include a semiconductor element, such as silicon (Si) or germanium (Ge). The third body layermay include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

410 401 410 410 420 410 420 420 420 420 410 420 2 2 The second BOX layermay be below the third body layer. For example, the second BOX layermay include SiO. However, the material of the second BOX layeris not limited to SiO. The second WGmay be arranged inside the second BOX layer. The second WGmay extend in the x-direction. For example, the second WGmay include SiNx. However, the material of the second WGis not limited to SiNx. For example, the second WGmay include Si. In the concept of WG, the second BOX layermay correspond to a clad layer and the second WGmay correspond to a core layer.

430 410 430 The optical passive device regionmay also be inside the second BOX layer. Optical passive devices may be arranged in the optical passive device region. Here, an optical passive device may refer to any device that changes the characteristics of light. For example, optical passive devices may include a light source, a light-to-current converter, a filter, a duplexer, an optical coupler, an interferometer, a spectrometer, etc.

430 440 400 200 440 230 230 200 440 430 u A wiring layer, a via, or a through electrode may be arranged below the optical passive device region. The second padmay be arranged at the bottom of the PIC chip, which overlaps the EIC chip. The second padmay be connected to the first pad, e.g. the first upper pad, of the EIC chip. The second padmay be connected to optical passive devices of the optical passive device regionthrough a wiring layer, a via, a through electrode, or the like.

440 400 230 200 440 230 400 200 400 200 u u Bonding between the second padof the PIC chipand the first upper padof the EIC chipmay correspond to pad-to-pad bonding. In general, pads include Cu, and thus, pad-to-pad bonding is referred to as Cu-to-Cu bonding. The bonding between the second padand the first upper padmay include insulator-to-insulator bonding in which a protective layer on the bottom surface of the PIC chipand a protective layer on the top surface of the EIC chipare bonded to each other. In this case, the PIC chipand the EIC chipmay be bonded to each other through hybrid copper bonding (HCB). HCB may refer to a combination of pad-to-pad bonding and insulator-to-insulator bonding.

400 420 320 300 330 600 500 As shown by the solid line arrow, an optical signal from the PIC chipmay be transmitted through the second WGand the first WGof the optical path bridge chip, reflected by the reflectorin the vertical direction, and transmitted to the outside through the multi-insulating layerand the transparent support layer.

420 400 320 300 The second WGof the PIC chipand the first WGof the optical path bridge chipmay transmit an optical signal through evanescent coupling. Here, evanescent coupling is also referred to as evanescent field coupling. In a dielectric single-mode WG, an optical signal has an evanescent electromagnetic field that decays exponentially out of a core. Accordingly, when two single-mode WGs are arranged to be adjacent to each other, a WG mode may be excited by the evanescent field of an adjacent core, thereby enabling transmission of an optical signal.

2 2 FIGS.A toC 2 FIG.A 2 FIG.B 2 FIG.A 2 FIG.C 2 FIG.B 2 2 FIGS.A andB 2 FIG.A 420 400 320 300 420 320 420 320 320 420 420 320 show a structure for the evanescent coupling between the second WGof the PIC chipand the first WGof the optical path bridge chip.is a perspective view of an evanescent coupling structure,is a plan view of the evanescent coupling structure of, andis a plan view of an evanescent coupling structure different from. As seen in, the second WGand the first WGmay have a tapered shape that thins toward an overlapping portion between the second WGand the first WG. For example, the first WGand the second WGmay respectively have tapered regions TPb and TPt, which may partially overlap each other in an overlapping region OL at end portions of the tapered regions TPb and TPt. Accordingly, as shown by the arrows in, an optical signal may be transmitted from the second WGto the first WGthrough evanescent coupling. An optical signal may be transmitted in a reverse direction through evanescent coupling.

2 FIG.B 2 FIG.C 2 FIG.C 320 420 320 1 2 1 320 2 420 1 2 1 2 2 2 In the evanescent coupling structure of, the tapered region TPb of the first WGand the tapered region TPt of the second WGmay have a constant angle of inclination as a whole. However, embodiments are not limited thereto, and for example, in the evanescent coupling structure of, a tapered region TPb′ of the first WGmay include a first tapered region TPband a second tapered region TPb, which may have different angles of inclination from each other. For example, the first tapered region TPbconnected to the central portion of the first WGmay have a greater angle of inclination than an angle of inclination of the second tapered region TPb. A tapered region TPt′ of the second WGmay include a first tapered region TPtand a second tapered region TPt. The first tapered region TPtmay have a greater angle of inclination than an angle of inclination of the second tapered region TPt. In the evanescent coupling structure of, the overlapping region OL may be formed in an end portion of each of the second tapered regions TPband TPt. This tapered evanescent coupling may be referred to as adiabatic coupling or adiabatic tapering in the sense that there is no loss.

1000 420 400 320 300 420 320 In the semiconductor packageof one or more embodiments, the coupling structure between the second WGof the PIC chipand the first WGof the optical path bridge chipis not limited to an evanescent coupling structure. For example, a butt coupling structure, in which the second WGis in direct contact with the first WG, may be used.

600 100 200 300 400 600 600 610 630 600 600 600 600 2 The multi-insulating layermay be arranged on the first redistribution substrateand may be adjacent to and surround the EIC chip, the optical path bridge chip, and the PIC chip. The multi-insulating layermay have a two-layer structure. For example, the multi-insulating layermay include a first insulating layerin a lower portion thereof and a second insulating layerin an upper portion thereof. For example, the multi-insulating layermay include SiO, silicon carbon nitride (SiCN), silicon oxynitride (SiON), SiN, or a polymer. However, the material of the multi-insulating layeris not limited to those mentioned above. The multi-insulating layermay be formed using a chemical vapor deposition (CVD) method or a spin coating method. However, a method of forming the multi-insulating layeris not limited to those mentioned above.

610 100 200 300 610 200 300 630 610 400 630 400 470 The first insulating layermay be arranged on the first redistribution substrateand may surround the side surfaces of the EIC chipand the optical path bridge chip. Due to manufacturing processes, a top surface of the first insulating layermay be substantially coplanar with a top surfaces of the EIC chipand the optical path bridge chip. The second insulating layermay be arranged on the first insulating layerand may be adjacent to and surround the side surface of the PIC chip. A top surface of the second insulating layermay be substantially coplanar with a top surface of the PIC chip, e.g., a top surface of a first bonding interface.

610 630 610 630 610 630 610 630 610 630 610 630 610 630 1000 1000 600 A material of the first insulating layermay be the same as or different from a material of the second insulating layer. Even when the material of the first insulating layeris the same as the material of the second insulating layer, the first insulating layerand the second insulating layermay have different material characteristics from each other due to a difference in manufacturing processes. For example, when the first insulating layerand the second insulating layerare formed using CVD under different CVD process conditions, a stress characteristic may be controlled to be different between the first insulating layerand the second insulating layerin terms of compressive strength or tensile stress. As described above, when the first insulating layerand the second insulating layerinclude different materials from each other or are controlled to have different material characteristics through manufacturing processes, there may be a boundary surface between the first insulating layerand the second insulating layer. In the semiconductor packageof one or more embodiments, the warpage characteristic of the semiconductor packagemay be improved by adjusting the stress characteristic of the multi-insulating layer.

630 630 630 630 2 2 The second insulating layermay provide an optical path. Accordingly, the second insulating layermay include a transparent material, such as SiO. However, the material of the second insulating layeris not limited to SiO. In one or more embodiments, a separate optical path block for an optical path may be arranged inside the second insulating layer.

500 400 600 500 200 300 400 1000 500 400 600 470 400 540 500 2 2 The transparent support layermay be arranged on the PIC chipand the multi-insulating layer. The transparent support layermay support main components, e.g., the EIC chip, the optical path bridge chip, and the PIC chip, of the semiconductor package. The transparent support layermay be attached to the PIC chipand the multi-insulating layerthrough a bonding interface BI. For example, the bonding interface BI may include the first bonding interfaceon the top surface of the PIC chipand a second bonding interfaceon the bottom surface of the transparent support layer. As seen from the solid line arrow, an optical signal needs to pass through the bonding interface BI, and therefore, the bonding interface BI may include a transparent material, such as SiOor SiCN. However, the material of the bonding interface BI is not limited to SiOor SiCN.

500 1000 500 500 400 600 2 In one or more embodiments, the transparent support layermay dissipate heat, which is generated in the semiconductor package, to the outside. In this case, to maximize the heat dissipation efficiency of the transparent support layer, the transparent support layermay be attached to the PIC chipand the multi-insulating layerthrough a thermal interface material (TIM). The TIM is a sort of adhesive and may include a material that is transparent and has a satisfactory heat transfer characteristic. For example, the TIM may include SiO, a polymer TIM, thermal grease, optic glue, or the like.

500 400 500 500 500 500 500 520 500 520 2 The transparent support layermay support optical communication of the PIC chip. Accordingly, the transparent support layermay include a material that transmits light. For example, the transparent support layermay include Si. However, the material of the transparent support layeris not limited to Si. For example, the transparent support layermay include SiO, glass, a transparent polymer, or the like. The transparent support layermay include a transparent material other than those materials mentioned above. To minimize the reflection of an optical signal, an anti-reflective layermay be arranged on the bottom surface of the transparent support layer. However, in some embodiments, the anti-reflective layermay be omitted.

600 430 400 330 320 300 420 400 500 500 A microlens may be formed in the multi-insulating layer. An optical signal may be received and collected through the microlens and transmitted to the optical passive device regionof the PIC chipthrough the reflectorand the first WGof the optical path bridge chipand the second WGof the PIC chip. In one or more embodiments, the microlens may not be formed in the transparent support layer. In the case of a semiconductor package for CPO, the semiconductor package is combined with a fiber assembly unit (FAU) that transmits an optical signal. When a microlens is not formed in the transparent support layer, the microlens may be arranged inside the FAU.

1000 200 400 300 200 300 320 330 320 420 400 400 320 420 320 330 500 1000 1000 1000 The semiconductor packageaccording to one or more embodiments may include the EIC chip, the PIC chip, and the optical path bridge chipadjacent to the EIC chip. The optical path bridge chipmay include the first WGand the reflector. The first WGmay be evanescent-coupled to the second WGof the PIC chip. Accordingly, an optical signal from the PIC chipmay be transmitted to the first WGthrough the evanescent coupling between the second WGand the first WG, reflected by the reflectorin the vertical direction, and transmitted to the outside through an upper portion, e.g., the transparent support layer, of the semiconductor package. Consequently, the semiconductor packageof one or more embodiments may facilitate the transmission of an optical signal. In addition, the components of the semiconductor packageof one or more embodiments may be more easily manufactured with compatibility with semiconductor package processes, and thus, the cost and yield of semiconductor packages may be significantly improved.

3 FIG. 1 2 FIGS.toC 1000 a is a cross-sectional view of a semiconductor packageaccording to one or more embodiments. Redundant descriptions given above with reference toare brief or omitted.

3 FIG. 1 FIG. 1 FIG. 1000 1000 200 400 1000 100 200 300 400 500 100 200 300 400 500 1000 450 200 400 300 450 a a Referring to, the semiconductor packageof one or more embodiments may be different from the semiconductor packageofin the connection structure of the EIC chipand the PIC chip. For example, the semiconductor packageof one or more embodiments may include the first redistribution substrate, the EIC chip, the optical path bridge chip, the PIC chip, and the transparent support layer. The first redistribution substrate, the EIC chip, the optical path bridge chip, the PIC chip, and the transparent support layerhave been described in the descriptions of the semiconductor packageof. However, because a connection terminalis between the EIC chipand the PIC chip, the optical path bridge chipmay become thicker by the height of the connection terminal.

1000 400 200 450 450 230 200 440 400 450 450 450 150 100 1000 a u 1 FIG. In the semiconductor packageof one or more embodiments, the PIC chipmay be connected to the EIC chipthrough the connection terminal. For example, the connection terminalmay be between the first upper padof the EIC chipand the second padof the PIC chip. For example, the connection terminalmay include solder. However, embodiments are not limited thereto, and for example, the connection terminalmay include a pillar and solder. The structure or material of the connection terminalhas been described in the description of the first external connection terminalof the first redistribution substrateof the semiconductor packageof.

400 200 450 460 400 200 460 1000 460 460 400 200 a Because the PIC chipis stacked on the EIC chipthrough the connection terminal, an adhesive layermay be arranged between the PIC chipand the EIC chip. For example, the adhesive layermay include a non-conductive film (NCF). An NCF is usually used as an adhesive layer when a semiconductor chip is bonded in a thermal compression bonding (TCB) manner in a semiconductor chip stacking process. However, in the semiconductor packageof one or more embodiments, the material of the adhesive layeris not limited to an NCF. In one or more embodiments, instead of the adhesive layer, an underfill may fill between the PIC chipand the EIC chip.

4 FIG. 1 FIG. 1 3 FIGS.to 2000 is a cross-sectional view of a system packageaccording to one or more embodiments.is also referred to, and redundant descriptions already given with reference toare brief or omitted.

4 FIG. 1 FIG. 1 FIG. 3 FIG. 2000 1000 1200 1300 1400 1500 1000 1000 1000 1000 2000 2000 1000 a Referring to, the system packageof one or more embodiments may include the semiconductor package, a base substrate, a first semiconductor device, a second semiconductor device, and a sealant. The semiconductor packagemay correspond to the semiconductor packageof. However, instead of the semiconductor packageof, the semiconductor packageofmay be applied to the system package. The system packageof one or more embodiments may also belong to a semiconductor package, system package may distinguish from the semiconductor packagethat is a component. The same concept may be applied to other system packages described below.

1200 1000 1300 1400 1200 2000 1200 The base substratemay support the semiconductor package, the first semiconductor device, and the second semiconductor device. The base substratemay correspond to an interposer or a package substrate. For example, in the system packageof one or more embodiments, the base substratemay correspond to an interposer.

1000 1300 1400 1200 1300 1200 1350 1400 1200 1450 1300 1000 1200 150 1300 1000 1300 1400 1200 The semiconductor package, the first semiconductor device, and the second semiconductor devicemay be mounted on the base substrate. For example, the first semiconductor devicemay be arranged on the central portion of the base substratein the x-direction via a third external connection terminal. The second semiconductor devicemay be arranged on the base substratevia a fourth external connection terminaland be on the left of the first semiconductor devicein the x-direction. The semiconductor packagemay be arranged on the base substratevia the first external connection terminaland be on the right of the first semiconductor devicein the x-direction. However, embodiments are not limited thereto, and for example, the positions of the semiconductor package, the first semiconductor device, and the second semiconductor deviceon the base substratemay be changed.

1200 1300 1400 1300 1400 1000 1200 1100 1200 1000 1300 1400 1100 2000 1200 1200 2000 1200 6 FIG. The base substratemay mediate signal transmission between the first semiconductor deviceand the second semiconductor deviceand signal transmission between each of the first and second semiconductor devicesandand the semiconductor package. The base substratemay be mounted on a package substrate (in). In this case, the base substratemay mediate transmission of signals, power, and the ground between the semiconductor package, the first semiconductor deviceor the second semiconductor deviceand the package substrate. In the system packageof one or more embodiments, the base substratemay correspond to a 2.5-dimensional (2.5D) interposer. Accordingly, the base substratemay include silicon (Si) and include a TSV therein. However, in the system packageof one or more embodiments, the base substrateis not limited to the 2.5D interposer.

An interposer may include a 2.5D interposer and a 2.3D interposer. In one or more embodiments, an interposer structure may be subdivided by including an Si bridge. Accordingly, a structure except for a 2.5D interposer may be referred to as a 2.xD interposer. A 2.5D interposer may refer to an Si interposer and may include a TSV therein. A 2.3D interposer may refer to an organic or inorganic interposer. In the case of an organic interposer, polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO) may be used as a body layer. In the case of an inorganic interposer, ceramic or glass may be used as a body layer. When the 2.3D interposer includes a through electrode, the through electrode may be referred to as a through dielectric via (TDV) or a through glass via (TGV) according to the material of the body layer. In one or more embodiments, the 2.3D interposer may be referred to as a panel level package (PLP) interposer or a re-distribution layer (RDL) interposer.

1200 1200 1200 1200 The base substratemay include a base body, a through electrode, and a wiring layer. For example, the base body may include Si, and accordingly, the base substratemay correspond to an Si interposer. The through electrode may extend through the base body. Because the base body includes Si, the through electrode may correspond to a TSV. The through electrode may extend to the wiring layer through the base body and may be connected to wires of the wiring layer. In one or more embodiments, the base substratemay include only a wiring layer therein but not a through electrode. The wiring layer may be arranged in an upper portion or a lower portion of the base body or in both the upper and lower portions of the base body. A substrate pad may be arranged on the top and bottom surfaces of the base substrate, and the through electrode may be connected to substrate pad directly or via the wiring layer.

1250 1200 1250 1200 1200 1100 1250 1250 1252 1254 1250 1250 150 100 1000 1 FIG. A second external connection terminalmay be arranged on the substrate pad on the bottom surface of the base substrateand electrically connected to the through electrode. The second external connection terminalmay be connected to the substrate pad on the top surface of the base substratevia the through electrode and the wiring layer. As described above, the base substratemay be mounted on the package substratevia the second external connection terminal. For example, the second external connection terminalmay include a pillarand solder. However, embodiments are not limited thereto, and for example, the second external connection terminalmay include only solder. The material of the second external connection terminalhas been described in the description of the first external connection terminalof the first redistribution substrateof the semiconductor packageof.

2000 1200 1000 1300 1400 1100 1000 1300 1400 1200 1200 In the system packageof one or more embodiments, the base substratemay be used for transmission of electrical signals among the semiconductor package, the first semiconductor device, and the second semiconductor deviceor used to transmit power or the ground from the package substrateto the semiconductor package, the first semiconductor device, and the second semiconductor device. Accordingly, the base substratemay not include devices, such as active devices or passive devices. However, embodiments are not limited thereto, and for example, the base substratemay include devices that control signal transmission.

1300 1200 1350 1300 1000 1200 1300 1400 1200 1300 1000 1400 1200 1300 1400 1400 1000 1300 1200 4 FIG. The first semiconductor devicemay be mounted on the base substratevia the third external connection terminal. As seen in, the first semiconductor devicemay be adjacent to the semiconductor packageand arranged on the left portion of the base substratein the x-direction. However, the first semiconductor devicemay be on the right of the second semiconductor devicein the x-direction on the base substrate. For example, the first semiconductor devicemay be between the semiconductor packageand the second semiconductor devicein the x-direction on the base substrate. In one or more embodiments, the positions of the first semiconductor deviceand the second semiconductor devicein the x-direction may be changed. For example, the second semiconductor devicemay be between the semiconductor packageand the first semiconductor devicein the x-direction on the base substrate.

1300 1300 The first semiconductor devicemay include a logic chip. Accordingly, the first semiconductor devicemay include a plurality of logic devices therein. For example, logic devices may include an AND gate, a NAND gate, an OR gate, a NOR gate, an exclusive OR (XOR) gate, an exclusive NOR (XNOR) gate, an inverter (INV), an adder (ADD), a delay (DLY), a filter (FIL), a multiplexer (MXT/MXIT), an OR/AND/inverter (OAI) gate, an AND/OR (AO) gate, an AND/OR/inverter (AOI) gate, a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, a counter, or a buffer. Logic devices may perform various kinds of signal processing, such as analog signal processing, analog-to-digital conversion, and control.

2000 1300 In the system packageof one or more embodiments, the first semiconductor devicemay be referred to as a central processing unit (CPU) chip, a microprocessor unit (MPU) chip, a graphics processing unit (GPU) chip, a neural processing unit (NPU) chip, a system-on-glass (SOG) chip, an application specific integrated circuit (ASIC) chip, an application processor (AP) chip, or a control chip, according to the operation thereof.

1300 1200 1300 The first semiconductor devicemay also include devices that support communication. However, embodiments are not limited thereto, and for example, the devices that support communication may be provided in a separate chip, e.g., a modem chip, and the separate chip may be arranged on the base substratein a structure coupled to the first semiconductor device.

1300 1300 1300 1300 1300 The first semiconductor devicemay include a chip body layer and an active layer. The active layer may be arranged below the chip body layer and may include an integrated circuit layer and a wiring layer. The integrated circuit layer may include the plurality of logic devices described above. The wiring layer may be arranged below the integrated circuit layer and may include multiple layers of wires. Accordingly, the bottom surface of the first semiconductor devicemay correspond to a front side that is an active surface, and the top surface of the first semiconductor devicemay correspond to a back side that is an inactive surface. For example, the bottom surface of the active layer may correspond to the front side of the first semiconductor device, and the top surface of the chip body layer may correspond to the back side of the first semiconductor device.

1400 1200 1450 1400 1300 1200 1400 1300 1400 1200 4 FIG. The second semiconductor devicemay be mounted on the base substratevia the fourth external connection terminal. As seen in, the second semiconductor devicemay be adjacent to the first semiconductor deviceand arranged on the left outer portion of the base substratein the x-direction. However, as described above, the position of the second semiconductor devicemay be switched with the position of the first semiconductor devicein the x-direction. In this case, the second semiconductor devicemay be on the left inner portion of the base substrate.

1400 1400 1400 1400 1400 1400 2000 1400 1400 For example, the second semiconductor devicemay include a volatile memory device, such as a dynamic random access memory (DRAM) device or a static RAM (SRAM) device, or a non-volatile memory device, such as a flash memory device, a phase-change RAM (PRAM) device, a magnetoresistive RAM (MRAM) device, a ferroelectric RAM (FeRAM) device, or a resistive RAM (RRAM) device. The second semiconductor devicemay correspond to a single chip or a package including a plurality of chips. For example, when the second semiconductor devicecorresponds to a single chip, the second semiconductor devicemay include one memory chip. When the second semiconductor devicecorresponds to a package, the second semiconductor devicemay include a plurality of memory chips. In the system packageof one or more embodiments, the memory chip of the second semiconductor devicemay include, for example, a DRAM chip. However, the type of memory chip of the second semiconductor deviceis not limited to the DRAM chip.

2000 1400 1400 1400 1400 1400 5 5 FIGS.A toC In the system packageof one or more embodiments, the second semiconductor devicemay include a high-bandwidth memory (HBM) package as a memory package. However, the second semiconductor deviceis not limited to the HBM package. For example, as a memory package, the second semiconductor devicemay have a general package structure. For example, the second semiconductor devicemay include an upper package substrate and a plurality of memory chips stacked on the upper package substrate. The memory chips may be stacked on the upper package substrate via a bonding wire or via a bump and a TSV. The single-chip structure or the package structure of the second semiconductor deviceis described in detail with reference to.

1500 1200 1000 1300 1400 1500 1200 1000 1200 1000 150 1500 1300 1400 1200 1300 1200 1400 1350 1450 1000 1300 1400 1500 1300 1400 1500 4 FIG. The sealantmay be on the base substrateand may seal the semiconductor package, the first semiconductor device, and the second semiconductor device. For example, the sealantmay be on the base substrateand may be adjacent to and surround the side surface of the semiconductor packageand fill between the base substrateand the semiconductor packageand between first external connection terminals. The sealantmay also be adjacent to and surround the side surface of each of the first semiconductor deviceand the second semiconductor deviceand fill between the base substrateand the first semiconductor device, between the base substrateand the second semiconductor device, between third external connection terminals, and between fourth external connection terminals. As shown in, the top surface of each of the semiconductor package, the first semiconductor device, and the second semiconductor devicemay be exposed by the sealant. However, embodiments are not limited thereto, and for example, the top surface of at least one of the first semiconductor deviceand the second semiconductor devicemay be covered by the sealant.

1500 1500 1500 1500 The sealantmay include an insulating material, for example, thermosetting resin such as epoxy resin, thermoplastic resin such as polyimide, or resin including a reinforcing material such as an inorganic filler. For example, the sealantmay include an Ajinomoto build-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT). The sealantmay include a molding material, such as an epoxy mold compound (EMC), or a photosensitive material, such as a photo-imageable encapsulant (PIE). However, the material of the sealantis not limited to those mentioned above.

5 5 FIGS.A toC 4 FIG. 1 4 FIGS.and 1 4 FIGS.to 2000 are detailed cross-sectional views showing the structures of a second semiconductor device of the system packageof.are also referred to, and redundant descriptions already given with reference toare brief or omitted.

5 FIG.A 2000 1400 2000 1400 1400 1200 1450 1450 Referring to, in the system packageof one or more embodiments, the second semiconductor devicemay include one memory chip. For example, the memory chip may include a volatile memory device, such as a DRAM device or an SRAM device, or a non-volatile memory device, such as a flash memory device. In the system packageof one or more embodiments, the memory chip of the second semiconductor devicemay include, for example, a DRAM chip. The second semiconductor devicemay be mounted on the base substratein a flip-chip bonding structure using the fourth external connection terminal. The fourth external connection terminalmay include a pillar and solder or only solder.

5 FIG.B 5 FIG.B 1400 1400 1410 1415 1410 1415 1410 1425 1430 1415 1400 2000 1415 1400 1400 1410 1415 1430 a a a a a Referring to, a second semiconductor devicemay include a semiconductor package having a wire bonding structure. For example, the second semiconductor devicemay include an upper package substrateand a plurality of memory chipsstacked on the upper package substrate. A memory chipmay be mounted on the upper package substratein a wire bonding structure using an adhesive layerand a wire. For example, the memory chipof the second semiconductor devicemay include a volatile memory chip, such as a DRAM chip or an SRAM chip, or a non-volatile memory chip, such as a flash memory chip. In the system packageof one or more embodiments, the memory chipof the second semiconductor devicemay include, for example, a DRAM chip. The second semiconductor devicemay include an inner sealant that is on the upper package substrateand seals the memory chipsand the wire. However, for convenience, the inner sealant is omitted from.

1415 1410 1415 1415 1415 1410 1415 1410 1400 1200 1450 5 FIG.B a Although four memory chipsare stacked on the upper package substratein, the number of memory chipsis not limited to 4. For example, three or less memory chipsor at least five memory chipsmay be stacked on the upper package substrate. The memory chipsare not limited to a step structure and may be stacked on the upper package substratein a zigzag structure or a structure combining a step structure and a zigzag structure. The second semiconductor deviceof a package structure may also be mounted on the base substratevia the fourth external connection terminal.

5 FIG.C 1400 1400 1410 1415 1410 1440 1410 1415 1430 1415 1415 1430 b b a a a a a a a a a Referring to, a second semiconductor devicemay include an HBM package. For example, the second semiconductor devicemay include a base chip, a plurality of core chipsstacked on the base chip, and an inner sealant. The base chipand the core chipsmay have a through electrodetherein. Among the core chips, the topmost core chipmay not have a through electrodetherein.

1410 1410 1410 1415 1415 1415 1410 1415 1415 a a a a a a a a a The base chipmay include logic devices. Accordingly, the base chipmay correspond to a logic chip. In this case, the base chipmay be below the core chipsand may combine and transmit the signals of the core chipsto the outside and transmit signals and power from the outside to the core chips. Accordingly, the base chipmay be referred to as a buffer chip or a control chip. Each of the core chipsmay correspond to a memory chip. For example, each of the core chipsmay correspond to a DRAM chip.

1415 1410 1415 a a a Each of the core chipsmay be stacked on the base chipor a core chiptherebelow through pad-to-pad bonding, HCB, bonding using a connection terminal, or bonding using an anisotropic conductive film (ACF). The ACF allows electricity to flow in only one direction and may refer to a conductive film that is formed by mixing fine conductive particles with adhesive resin.

1415 1410 1440 1415 1440 1415 1440 a a a a The core chipson the base chipmay be sealed by the inner sealant. However, the top surface of the topmost core chipmay not be covered and exposed by the inner sealant. However, embodiments are not limited thereto, and for example, the top surface of the topmost core chipmay be covered by the inner sealant.

1415 1410 1415 1415 1410 1450 1410 1400 1200 1450 a a a a a a b 5 FIG.C Although the twelve core chipsare stacked on the base chipin, the number of core chipsis not limited to 12. For example, eleven or less or at least 13 core chipsmay be stacked on the base chip. The fourth external connection terminalmay be arranged on the bottom surface of the base chip. Accordingly, the second semiconductor deviceof the HBM package may also be mounted on the base substratevia the fourth external connection terminal.

6 7 FIGS.and 1 4 FIGS.and 1 5 FIGS.toC are cross-sectional views of system packages according to embodiments.are also referred to, and redundant descriptions already given with reference toare brief or omitted.

6 FIG. 1 FIG. 1 FIG. 3 FIG. 4 FIG. 4 FIG. 2000 1000 1100 1200 1300 1400 1500 1000 1000 1000 1000 2000 1200 1300 1400 1500 2000 1200 1200 2000 a a a Referring to, a system packagemay include the semiconductor package, the package substrate, an interposer, the first semiconductor device, the second semiconductor device, and the sealant. The semiconductor packagemay correspond to the semiconductor packageof. However, instead of the semiconductor packageof, the semiconductor packageofmay be applied to the system packageof one or more embodiments. The interposer, the first semiconductor device, the second semiconductor device, and the sealanthave been described in the description of the system packageof. The interposermay correspond to the base substrateof the system packageof.

2000 1100 1100 2000 1100 1100 a a In the system packageof one or more embodiments, the package substratemay include, for example, a ceramic substrate, a printed circuit board (PCB), a glass substrate, an interposer substrate, or the like. In one or more embodiments, the package substratemay include an active wafer such as a silicon wafer. In the system packageof one or more embodiments, the package substratemay include a PCB. However, the package substrateis not limited to the PCB.

1100 1100 1100 The package substratemay include a substrate body layer, a protective layer, and a substrate pad. The substrate body layer may form the body of the package substrateand may include a wiring layer therein. For example, when the package substrateincludes a PCB, the substrate body layer may include a core layer and a wiring layer.

For example, the core layer may include glass fiber, such as FR-4, and resin. The core layer may include BT resin, polycarbonate (PC) resin, a build-up film such as an ABF, or laminate resin.

The wiring layer may be divided into an upper wiring layer and a lower wiring layer by the core layer. Each of the upper wiring layer and the lower wiring layer may include multiple layers of wires. The number of layers of wires in the upper wiring layer may be the same as or different from the number of layers of wires in the lower wiring layer. The wiring layer may include multiple layers of wires, an interlayer insulating layer insulating the wires from each other, and a vertical via connecting wires in different layers to each other. For example, the wires and the vertical via may include copper (Cu). However, the material of the wires and the vertical via is not limited to Cu. For example, the interlayer insulating layer may include prepreg (PPG). However, the material of the interlayer insulating layer is not limited to the PPG.

1100 In one or more embodiments, the core layer may be omitted. In one or more embodiments, the package substratemay correspond to a redistribution substrate. In this case, the substrate body layer may not include a separate core layer and may include an interlayer insulating layer of PID resin and multiple layers of wires.

The protective layer may be arranged on the top and bottom surfaces of the substrate body layer. For example, the protective layer may include solder resist (SR). However, the material of the protective layer is not limited to the SR. The substrate pad may be arranged on the top and bottom surface of the substrate body layer. The substrate pad may pass through the protective layer. The substrate pad may be connected to wires of the wiring layer of the substrate body layer.

1150 1250 1150 2000 1150 1150 a An external connection terminalmay be arranged on the substrate pad on the bottom surface of the substrate body layer. The second external connection terminalmay be arranged on the substrate pad on the top surface of the substrate body layer. The external connection terminalmay connect the system packageto a package substrate of an external system or a main board of an electronic device such as a mobile device. For example, the external connection terminalmay include solder. The material of the external connection terminalis not limited to the solder.

7 FIG. 1 FIG. 1 FIG. 3 FIG. 2000 1000 1 1000 2 1200 1600 1000 1 1000 2 1000 1000 1000 2000 b a a b Referring to, a system packageof one or more embodiments may include two semiconductor packages (e.g.,-and-), a base substrate, and an optical fiber. Each of the two semiconductor packages (-and-) may correspond to the semiconductor packageof. However, instead of the semiconductor packageof, the semiconductor packageofmay be applied to the system packageof one or more embodiments.

2000 1200 1000 1 1000 2 1200 2000 2000 b a a a 4 6 FIGS.and In the system packageof one or more embodiments, the base substratemay support the two semiconductor packages (-and-). The base substratemay correspond to an interposer, a package substrate, or a support block substrate. The interposer and the package substrate have been described in the description of the system packagesandof. Because the support block substrate serves as a support, a component may not be arranged in the support block substrate. Accordingly, the support block substrate may include Si, glass, ceramic, a polymer, or the like, and a component such as a wire may not be inside the support block substrate.

2000 1000 1 700 1 1000 2 700 2 700 1 700 2 1600 1000 1 1000 2 1600 2000 1600 b b In the system packageof one or more embodiments, a first semiconductor package-may include a first optical coupler-, and a second semiconductor package-may include a second optical coupler-. The first optical coupler-and the second optical coupler-may be optically coupled to the optical fiber. Accordingly, optical communication may be implemented between the first semiconductor package-and the second semiconductor package-through the optical fiber. In the system packageof one or more embodiments, the optical fibermay include an FAU that transmits optical signals.

1000 1 1000 2 1200 2000 1200 1300 1400 2000 1200 1200 a b a a a 4 FIG. Although the two semiconductor packages (-and-) are arranged on the base substratein the system packageof one or more embodiments, the number of semiconductor packages on the base substrateis not limited to 2. Apart from a semiconductor package, the first and second semiconductor devicesandof the system packageofmay be arranged on the base substrate. In this case, the base substratemay correspond to an interposer or a package substrate.

8 8 FIGS.A toL 1 FIG. 1 7 FIGS.to are schematic cross-sectional views of stages in a method of manufacturing a semiconductor package, according to one or more embodiments.is also referred to, and redundant descriptions already given with reference toare brief or omitted.

8 FIG.A 500 500 500 500 1000 500 500 Referring to, in the method of one or more embodiments, a carrier substrateS may be prepared. The carrier substrateS may include Si. The carrier substrateS may serve as a support substrate during stages in the method of manufacturing a semiconductor package and may become the transparent support layerof the semiconductor packagein the final stage. The carrier substrateS may have a wafer-level size and correspond to a plurality of transparent support layers.

8 FIG.B 1 FIG. 8 FIG.B 500 520 540 500 520 540 1000 520 540 520 Referring to, after the carrier substrateS is formed, an anti-reflective layerS and a second bonding interfaceS may be formed on the top surface of the carrier substrateS. The anti-reflective layerS and the second bonding interfaceS have been described in the description of the semiconductor packageof. However, in the stage of, the anti-reflective layerS and the second bonding interfaceS may each have a wafer-level size. In one or more embodiments, the anti-reflective layerS may be omitted.

500 1000 500 500 500 1 FIG. Compared to the transparent support layerof the semiconductor packageof, the carrier substrateS may be upside down. Accordingly, the top surface of the carrier substrateS may correspond to the bottom surface of the transparent support layer.

8 FIG.C 1 FIG. 400 500 400 470 400 540 500 400 540 1000 Thereafter, referring to, PIC chipsmay be bonded to and stacked on the carrier substrateS. Each of the PIC chipsmay be stacked through bonding between the first bonding interfaceon the bottom surface of each PIC chipand the second bonding interfaceS of the carrier substrateS. The PIC chipand the second bonding interfaceS have been described in the description of the semiconductor packageof.

8 FIG.D 400 630 500 400 630 400 500 Referring to, after the PIC chipsare stacked, a second insulating layerS may be formed on the carrier substrateS to be provided on and cover the side surfaces of the PIC chips. The second insulating layerS may have a wafer-level size and cover side surfaces of all the PIC chipson the carrier substrateS.

630 400 8 FIG.C 2 2 The process of forming the second insulating layerS is described in detail below. Firstly, a second insulating material layer may be applied to the resultant structure ofto cover the top and side surfaces of the PIC chips. The second insulating material layer may be applied using CVD or spin coating. For example, the second insulating material layer may include SiO, SiCN, SiON, SiN, or a polymer. In the case of SiO, SiCN, SiON, or SiN, CVD may be used. In the case of a polymer, spin coating may be used.

400 630 400 630 630 400 An upper portion of the second insulating material layer may be removed to expose the top surfaces of the PIC chips. The upper portion of the second insulating material layer may be removed by etching and/or chemical mechanical polishing. The second insulating layerS may be completed by removing the upper portion of the second insulating material layer. Accordingly, the top surfaces of the PIC chipsmay be exposed by the second insulating layerS. The top surface of the second insulating layerS may be substantially coplanar with the top surfaces of the PIC chips.

8 FIG.E 1 FIG. 630 200 300 400 630 200 400 300 400 320 300 420 400 200 300 1000 200 400 450 a a a a Referring to, after the second insulating layerS is formed, EIC chipsand optical path bridge chipsmay be stacked on the PIC chipsand the second insulating layerS. Each of the EIC chipsmay be stacked on a PIC chipcorresponding thereto through pad-to-pad bonding or HCB. Each of the optical path bridge chipsmay be stacked on a PIC chipcorresponding thereto through insulator-to-insulator bonding. The first WGof each optical path bridge chipmay be coupled to the second WGof the PIC chipin a structure for evanescent coupling. The other descriptions of the EIC chipand the optical path bridge chiphave been given in the description of the semiconductor packageof. In one or more embodiments, the EIC chipmay be stacked on the PIC chipthrough the connection terminal.

8 FIG.F 200 300 610 400 630 200 300 610 200 300 400 630 610 630 a a a Referring to, after the EIC chipsand the optical path bridge chipsare stacked, a first insulating layerS may be formed on the PIC chipsand the second insulating layerS to be provided on and cover the side surfaces of the EIC chipsand the side surfaces of the optical path bridge chips. The first insulating layerS may have a wafer-level size and cover the side surfaces of all the EIC chipsand the side surfaces of all the optical path bridge chipson the PIC chipsand the second insulating layerS. The method of forming the first insulating layerS may be similar to the method of forming the second insulating layerS.

610 200 300 610 200 300 8 FIG.E a a The process of forming the first insulating layerS is described in detail below. Firstly, a first insulating material layer may be applied to the resultant structure ofto be provided on and cover the top and side surfaces of the EIC chipsand the optical path bridge chips. Thereafter, the first insulating layerS may be completed by removing an upper portion of the first insulating material layer to expose the top surfaces of the EIC chipsand the optical path bridge chips.

610 630 610 630 610 630 610 630 610 630 610 630 610 630 The material of the first insulating layerS may be the same as or different from the material of the second insulating layerS. Even when the material of the first insulating layerS is the same as the material of the second insulating layerS, the first insulating layerS and the second insulating layerS may have different material characteristics from each other due to a difference in manufacturing processes For example, when the first insulating layerS and the second insulating layerS are formed using CVD under different CVD process conditions, the stress characteristic may be controlled to be different between the first insulating layerS and the second insulating layerS with respect to compressive strength or tensile stress. When the first insulating layerS and the second insulating layerS include different materials from each other or are controlled to have different material characteristics through manufacturing processes, there may be a boundary surface between the first insulating layerS and the second insulating layerS.

8 FIG.G 610 220 200 220 a Referring to, after the first insulating layerS is formed, a process may be performed to expose the through electrodeof each of the EIC chips. The process of exposing the through electrodemay be carried out through a grinding process and an Si recess process.

220 201 200 220 220 201 a The process of exposing the through electrodeis described in detail below. Firstly, an upper portion of the first body layerof each EIC chipmay be primarily removed by a grinding process. At this time, the through electrodemay not be exposed. Thereafter, the through electrodemay be exposed by additionally removing an upper portion of the first body layerby using an Si recess process. For example, the Si recess process may be carried out through a dry etching process. However, embodiments are not limited thereto, and for example, a wet etching process may be used for the Si recess process.

200 200 220 201 220 300 610 300 610 b a 8 FIG.G After the grinding process and the Si recess process, EIC chipshaving less thickness than the EIC chipsmay be formed. After the Si recess process, the through electrodemay slightly protrude from the top surface of the first body layer. However, for convenience, it is illustrated inthat the through electrodedoes not protrude. The grinding process and the Si recess process may also be performed on the optical path bridge chipsand the first insulating layer. Accordingly, after the grinding process and the Si recess process, the optical path bridge chipsand the first insulating layerS may also be thinner.

8 FIG.H 1 FIG. 220 240 200 300 610 240 200 300 610 240 1000 240 240 201 200 a a c. Referring to, after the through electrodeis exposed, a protective layerS may be formed on the EIC chips, the optical path bridge chips, and the first insulating layerS. The protective layerS may be provided on and cover all of the EIC chips, the optical path bridge chips, and the first insulating layerS. The other descriptions of the protective layerS have been given in the description of the semiconductor packageof. The protective layerS may form the protective layeron the first body layerin each of EIC chips

8 FIG.I 1 FIG. 240 230 230 200 230 240 220 230 1000 200 230 d c d d d Referring to, after the protective layerS is formed, the first pad, e.g., the first lower pad, may be formed on each of the EIC chips. The first lower padmay pass through the protective layerS and may be connected to the through electrode. The first lower padhas been described in the description of the semiconductor packageof. EIC chipsmay be completed by forming the first lower pad.

8 FIG.J 1 FIG. 230 100 230 240 100 100 1000 d d Referring to, after the first lower padis formed, a redistribution substrateS may be formed on the first lower padand the protective layerS. The redistribution substrateS may have a wafer-level size. The description of the redistribution substrateS has been given in the description of the semiconductor packageof.

8 FIG.K 1 FIG. 100 150 100 150 1000 Referring to, after the redistribution substrateS is formed, the first external connection terminalmay be formed on the redistribution substrateS. The first external connection terminalhas been described in the description of the semiconductor packageof.

8 FIG.L 1 FIG. 3 FIG. 8 FIG.I 8 FIG.L 1000 1000 1000 200 400 450 1000 3000 3000 3000 a a Referring to, the semiconductor packagemay be manufactured by singulation using a sawing process S. For example, the semiconductor packagemay correspond to the semiconductor packageof. When each of the EIC chipsis stacked on a PIC chipvia the connection terminal, the semiconductor packageofmay be manufactured in the stage of. The singulation using the sawing process may be carried out in a ring mount. The ring mountmay include a support ring and a dicing tap provided on and covering an opening of the support ring. For convenience, only the dicing tape of the ring mountis illustrated in.

9 9 FIGS.A toI 1 FIG. 1 8 FIGS.toL are schematic cross-sectional views of stages in a method of manufacturing an optical path bridge chip, according to one or more embodiments.is also referred to, and redundant descriptions already given with reference toare brief or omitted.

9 FIG.A 1 FIG. 300 300 301 310 301 310 1000 a a Referring to, in the method of manufacturing an optical path bridge chip, a waferS having a silicon-on-insulator (SOI) structure may be prepared. The waferS may include the second body layerand a first BOX layer. The descriptions of the second body layerand the first BOX layerhave been given in the description of the semiconductor packageof.

9 FIG.B 310 310 1 310 1 301 1 320 a b a Referring to, the first BOX layermay be patterned by a photolithography process. A first BOX layerhaving a first trench Tmay be formed by patterning the first BOX layer. The first trench Tmay expose the top surface of the second body layer. The first trench Tmay have a width corresponding to the width of the first WG, which is formed later, in the y-direction.

9 FIG.C 1 301 1 301 301 ei ei ei Referring to, after the first trench Tis formed, an initial support epitaxial layermay be formed in the first trench T. The initial support epitaxial layermay be formed by epitaxial growth. Accordingly, the initial support epitaxial layermay include Si.

9 FIG.D 9 FIG.D 301 301 301 301 301 301 ei e ei ei e Referring to, after the initial support epitaxial layeris formed, a support epitaxial layermay be formed by an etching process. In the etching process, the initial support epitaxial layermay be rapidly etched in one direction based on the crystal lattice structure of the initial support epitaxial layerso that the support epitaxial layerhaving a slope at an angle with respect to an upper surface of the second body layermay be formed, as shown in.

9 FIG.E 330 301 301 e e Referring to, continuously, the reflectormay be formed by forming a metal plate on the support epitaxial layer. For example, the metal plate on the support epitaxial layermay be formed by physical vapor deposition (PVD).

9 FIG.F 330 1 1 310 2 c. Referring, after the reflectoris formed, the remaining portion of the first trench Tmay be filled using a gapfill process. For example, the gapfill process may be carried out by CVD. In the gapfill process, the remaining portion of the first trench Tmay be filled by the material, e.g., SiO, of a first BOX layer

9 FIG.G 310 310 2 310 2 320 2 310 2 310 2 330 330 c d c c d Referring to, the first BOX layermay be patterned by a photolithography process. A first BOX layerhaving a second trench Tmay be formed by patterning the first BOX layer. The second trench Tmay be formed in a portion in which the first WGis formed. The second trench Tmay be formed by removing an upper portion of the first BOX layer. Accordingly, the bottom of the second trench Tmay still be a part of the first BOX layer. The right end of the second trench Tin the x-direction may not be in contact with the reflectorbut be separated from the reflector.

9 FIG.H 2 320 2 320 2 Referring to, after the second trench Tis formed, the first WGmay be formed on the bottom of the second trench T. The first WGmay be formed by depositing a WG material, e.g., SiN, on the bottom of the second trench Tto a uniform thickness by using CVD.

9 FIG.I 9 9 FIGS.A toH 320 2 2 310 2 300 2 d Referring to, after the first WGis formed, the remaining portion of the second trench Tmay be filled using a gapfill process. For example, the gapfill process may be carried out by CVD. In the gapfill process, the remaining portion of the second trench Tmay be filled by the material, e.g., SiO, of the first BOX layer. An optical path bridge chip may be completed by filling the second trench T. However, because the processes ofare formed at a wafer level, the optical path bridge chipmay be completely formed by singulation using a sawing process.

While embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.