System and Method for Selectively Allocating Entries at a Branch Target Buffer

1. A data processing system, comprising: a processor to execute processor instructions; a branch target buffer having a plurality of entries, each entry to store a branch instruction address and a corresponding branch target address; programmable storage circuitry to store a first value, the programmable storage circuitry distinct from the plurality of entries of the branch target buffer; and control circuitry to determine whether to create an entry at the branch target buffer corresponding to a first branch instruction based on comparing the first value to a portion of a branch instruction address of the first branch instruction, wherein the control circuitry is further configured to compare the first value and the portion of a branch instruction address for equality in response to one or more indicator control bits stored in a control register of the programmable storage circuitry having a first value and for inequality in response to the one or more indicator control bits having a second value.

2. A data processing system, comprising: a processor to execute processor instructions; a branch target buffer having a plurality of entries, each entry to store a branch instruction address and a corresponding branch target address; programmable storage circuitry to store a first value, the programmable storage circuitry distinct from the plurality of entries of the branch target buffer; and control circuitry to determine whether to create an entry at the branch target buffer corresponding to a first branch instruction based on comparing the first value to a portion of a branch instruction address of the first branch instruction and one or more indicator control bits stored in a control register of the programmable control storage circuitry, wherein determining whether to create an entry at the branch target buffer corresponding to the first branch instruction based on comparing the first value to the portion of the branch instruction address of the first branch instruction further comprises creating the entry based on determining the first value is equal to a value represented by the portion of the branch instruction address when the one or more indicator control bits have a first indicator value and based on determining that the branch target buffer does not include an existing entry corresponding to the first branch instruction.

3. The system of claim 1 , wherein the control register includes a randomize indicator, wherein assertion of the randomize indicator causes the control circuitry to generate the first value.

4. The system of claim 1 , wherein the programmable storage circuitry is further to store a second value specifying a number of bits to represent the first value.

5. The system of claim 1 , wherein the first value and the portion of the branch instruction address each includes four or fewer bits.

6. The system of claim 2 , wherein determining whether to create an entry at the branch target buffer corresponding to the first branch instruction based on comparing the first value to the portion of the branch instruction address of the first branch instruction further comprises creating the entry based on determining the first value is not equal to a value represented by the portion of the branch instruction address when the one or more indicator control bits have a second indicator value and based on determining that the branch target buffer does not include an existing entry corresponding to the first branch instruction.

7. The system of claim 6 , wherein the control register includes a randomize indicator at the programmable storage circuitry, wherein assertion of the randomize indicator causes the control circuitry to generate the first value.

8. The system of claim 6 , wherein the programmable storage circuitry is further to store a second value specifying a number of bits to represent the first value.

9. The system of claim 6 , wherein the first value and the portion of the branch instruction address each includes four or fewer bits.

10. A method comprising: receiving, by a processor, a branch instruction and a corresponding branch instruction address; receiving at control circuitry a first value stored in programmable storage circuitry; comparing, by the control circuitry, the first value to a portion of the branch instruction address; and determining, by the control circuitry, whether to create an entry at a branch target buffer corresponding to the branch instruction based on a result of the comparing and one or more indicator control bits stored in a control register of the programmable control storage circuitry, wherein determining whether to create an entry at the branch target buffer corresponding to the branch instruction based on a result of the comparing and the one or more indicator control bits further comprises creating the entry in response to determining the first value is not equal to the portion of the branch instruction address when the one or more indicator control bits have a first indicator value and based on determining that the branch target buffer does not include an existing entry corresponding to the branch instruction.

11. The method of claim 10 , wherein determining whether to create an entry at the branch target buffer corresponding to the branch instruction based on a result of the comparing further comprises creating the entry in response to determining the first value is equal to the portion of the branch instruction address when the one or more indicator control bits have a second indicator value and based on determining that the branch target buffer does not include an existing entry corresponding to the branch instruction.

12. The method of claim 10 , wherein comparing further comprises comparing a predetermined number of bits of the first value to the portion of the branch instruction address, the number of bits specified by a second value at the programmable storage circuitry.

13. The method of claim 10 , wherein the first value is a random value generated in response to assertion of randomize indicator at the programmable storage location.

14. The method of claim 10 , wherein the first value and the portion of the branch instruction address each includes four or fewer bits.

15. The method of claim 10 , wherein the programmable storage circuitry is distinct from the plurality of entries.

16. A method comprising: receiving, by a processor, a branch instruction and a corresponding branch instruction address; receiving at control circuitry a first value stored in a programmable storage circuitry; comparing, by the control circuitry, the first value to a portion of the branch instruction address; and determining, by the control circuitry, whether to create an entry at a branch target buffer corresponding to the branch instruction based on a result of the comparing, wherein comparing further comprises comparing for equality in response to one or more indicator control bits stored in a control register of the programmable storage circuitry having a first value or comparing for inequality in response to the one or more indicator control bits having a second value.

17. The method of claim 16 , wherein comparing further comprises comparing a predetermined number of bits of the first value to the portion of the branch instruction address, the number of bits specified by a second value at the programmable storage circuitry.

18. The method of claim 16 , wherein the first value is a random value generated in response to assertion of a randomize indicator at the programmable storage circuitry.

19. The method of claim 16 , wherein the first value and the portion of the branch instruction address each includes four or fewer bits.

20. The method of claim 16 , wherein the programmable storage circuitry is distinct from the plurality of entries.

21. A branch target buffer, comprising: a plurality of entries, each entry including storage locations to store a branch instruction address and a branch target address corresponding to the branch instruction; an allocation control register to store a first value; and control circuitry to determine whether to create a first entry of the plurality of entries corresponding to a first branch instruction in response to comparing the first value from said allocation control register to a portion of an instruction address of the first branch instruction, wherein the allocation control register further includes one or more indicator control bits, and wherein comparing further comprises comparing for equality in response to the one or more indicator control bits having a first value or comparing for inequality in response to the one or more indicator control bits having a second value.

22. The branch target buffer of claim 21 , wherein the allocation control register further includes a second value, the second value indicating a number of bits of the first value to compare with the portion of the branch instruction address.

23. The branch target buffer of claim 21 , wherein the allocation control register further includes a randomized control bit, and wherein the first value is a random value generated in response to assertion of the randomized control bit.

24. The branch target buffer of claim 21 , wherein the allocation control register is distinct from the plurality of entries.