Early Power Compensation Method And Apparatus Thereof

1. A method, comprising: receiving power from a power source; regulating the received power to provide regulated power to a processor via a power delivery network; determining whether one or more processing units of a plurality of processing units of the processor are starting; and adjusting an amount of the regulated power provided to the plurality of processing units before the one or more processing units are started responsive to a determination that the one or more processing units are starting, wherein the adjusting of the amount of the regulated power provided to the plurality of processing units before the one or more processing units are started comprises charging at least one decoupling capacitor of one or more decoupling capacitors of the power delivery network for at least an amount of charging time proportional to a quantity of the one or more processing units that are starting.

2. The method of claim 1 , wherein the determining of whether the one or more processing units are starting comprises receiving, via a serial bus, a signal indicating that the one or more processing units are starting.

3. The method of claim 2 , wherein the adjusting of the amount of the regulated power provided to the plurality of processing units before the one or more processing units are started further comprises increasing the power provided to the plurality of processing units at least a period of time before the one or more processing units are started, and wherein the period of time is based at least in part on a speed of the serial bus, an amount of charging time for charging one or more decoupling capacitors, a quantity of the one or more processing units that are starting, or a combination thereof.

4. The method of claim 1 , wherein the adjusting of the amount of the regulated power provided to the plurality of processing units further comprises: determining, using a lookup table, an amount of power increase and an amount of time for the power increase based on a quantity of the one or more processing units that are starting; and increasing the power provided to the plurality of processing units by the determined amount of power increase and for the determine amount of time.

5. The method of claim 1 , wherein the adjusting of the amount of the regulated power provided to the plurality of processing units further comprises adjusting a voltage, an operating frequency, a system clock, or a combination thereof to increase the power provided to the plurality of processing units.

6. The method of claim 1 , further comprising: receiving a feedback on the power provided to the plurality of processing units via a single-ended feedback line.

7. An apparatus, comprising: a power management circuit; a processor comprising a plurality of processing units; a serial bus coupled between the power management circuit and the processor; and a power delivery network coupled between the power management circuit and the processor, wherein the processor is configured to determine whether one or more processing units of the plurality of processing units are starting, wherein the power management circuit is further configured to adjust an amount of the regulated power provided to the processor before the one or more processing units are started responsive to a determination by the processor that the one or more processing units are starting, wherein the power management circuit is configured to receive and regulate power from a power source and provide regulated power to the processor via the power delivery network, wherein the power delivery network comprises one or more decoupling capacitors, and wherein, in adjusting the amount of the regulated power provided to the processor before the one or more processing units are started, the power management circuit is configured to charge at least one decoupling capacitor of the one or more decoupling capacitors for at least an amount of charging time proportional to a quantity of the one or more processing units that are starting.

8. The apparatus of claim 7 , wherein the power management circuit is configured to receive, from the processor via the serial bus, a signal indicating that the one or more processing units are starting, and wherein the serial bus comprises an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a system management bus (SMB), or a serial low-power inter-chip media bus (SLIMbus).

9. The apparatus of claim 7 , wherein, in adjusting the amount of the regulated power provided to the processor before the one or more processing units are started, the power management circuit is configured to increase an amount of the regulated power provided to the processor at least a period of time before the one or more processing units are started.

10. The apparatus of claim 9 , wherein the period of time is based at least in part on a speed of the serial bus, an amount of charging time for charging at least one decoupling capacitor of the one or more decoupling capacitors of the power delivery network, a quantity of the one or more processing units that are starting, or a combination thereof.

11. The apparatus of claim 7 , wherein, in adjusting the amount of the regulated power provided to the processor before the one or more processing units are started, the power management circuit is configured to perform operations comprising: determining, using a lookup table, an amount of power increase and an amount of time for the power increase based on a quantity of the one or more processing units that are starting; and increasing the amount of regulated power provided to the processor by the determined amount of power increase and for the determine amount of time.

12. The apparatus of claim 7 , wherein, in adjusting the amount of the regulated power provided to the processor before the one or more processing units are started, the power management circuit is configured to adjust a voltage, an operating frequency, a system clock, or a combination thereof with respect to the regulated power provided to the processor.

13. The apparatus of claim 7 , wherein a height of the one or more decoupling capacitors is less than 1.25 mm, and wherein the amount of charging time is at least an amount of time that allows the at least one decoupling capacitor to be charged to compensate for less than 12% voltage droop, as measured from a steady-state voltage level, when the one or more processing units are started.

14. The apparatus of claim 7 , wherein the power management circuit is enclosed in a first integrated-circuit (IC) package, wherein the power management circuit comprises an error amplifier having a first input port and a second input port, wherein the first input port is connected to a power ball or a power pin of the first IC package, and wherein the second input port is connected to a local ground plane of the first IC package.

15. The apparatus of claim 7 , further comprising: a multi-layer board on which the processor is disposed, wherein the power delivery network comprises a single-ended feedback line disposed in the board and coupled between the power management circuit and the processor, and wherein the power management circuit is configured to receive, via the feedback line, a feedback on the regulated power provided to the processor.

16. The apparatus of claim 15 , wherein the power management circuit is enclosed in a first integrated-circuit (IC) package and the processor is enclosed in a second IC package, wherein the first IC package and the second IC package are disposed on a top layer of the board, wherein the board comprises a separate power ball pad or a separate power finger on the top layer thereof, wherein the feedback line is coupled between a power ball or a power pin associated with the first IC package and the separate power ball pad or the separate power finger on the top layer of the board, and wherein the separate power ball pad or the separate power finger on the top layer of the substrate is connected to a separate power ball or a separate power pin associated with the second IC package.

17. The apparatus of claim 15 , wherein the power delivery network comprises one or more decoupling capacitors, and wherein at least one decoupling capacitor of the one or more decoupling capacitors is mounted on the board in a single-sided component placement (SSCP) configuration with respect to the processor.

18. The apparatus of claim 15 , wherein the power delivery network comprises a power plane and a ground plane, and wherein the feedback line is electromagnetically shielded from external noise with the power plane, the ground plane, or both the power plane and the ground plane of the power delivery network.

19. The apparatus of claim 18 , wherein a width of the feedback line is no more than 8 mil, and wherein at least a space between the feedback line and the power plane or a space between the feedback line and the ground plane is no more than 8 mil.