Translation Lookaside Buffer Switch Bank

1. A device comprising: a processor; a plurality of translation lookaside buffers, wherein each of the plurality of translation lookaside buffers is to be assigned to a different process of a plurality of processes of the processor; a plurality of switches, wherein each of the plurality of switches comprises a register for storing a different process identifier of a plurality of process identifiers, wherein each of the plurality of switches is associated with a different translation lookaside buffer of the plurality of translation lookaside buffers; and a memory management unit for: ranking the plurality of processes based on a memory utilization, wherein the ranking is used to assign one or more of the plurality of translation lookaside buffers to one or more of the plurality of processes; receiving a virtual memory address and a process identifier from the processor; and forwarding the process identifier to the plurality of switches, wherein each switch of the plurality of switches is further for connecting the memory management unit to a translation lookaside buffer of the plurality of translation lookaside buffers that is associated with the each switch when there is a match between the process identifier and the different process identifier stored by the register of the each switch.

2. The device of claim 1 , wherein the memory management unit is further for: accessing one of the plurality of translation lookaside buffers when the memory management unit is connected to the one of the plurality of translation lookaside buffers by one of the plurality of switches; and searching for an entry that maps the virtual memory address to a physical memory address in the one of the plurality of translation lookaside buffers.

3. The device of claim 2 , wherein the memory management unit is further for: retrieving the physical memory address, when the entry that maps the virtual memory address to the physical memory address is found; and accessing the physical memory address in a memory device.

4. The device of claim 2 , wherein the memory management unit is further for: retrieving the physical memory address, when the entry that maps the virtual memory address to the physical memory address is found; and searching a memory cache for an entry associated with the physical memory address.

5. The device of claim 2 , wherein the memory management unit is further for: accessing a level 2 translation lookaside buffer to find the entry that maps the virtual memory address to the physical memory address, when the entry that maps the virtual memory address to the physical memory address is not found in the one of the plurality of translation lookaside buffers.

6. The device of claim 2 , wherein the memory management unit is further for: performing a page walk in a page table stored in a memory device to find the entry that maps the virtual memory address to the physical memory address, when the entry that maps the virtual memory address to the physical memory address is not found in the one of the plurality of translation lookaside buffers.

7. The device of claim 1 , further comprising: an open collector line coupled to the plurality of switches; an additional switch controlled by the open collector line; and an additional translation lookaside buffer, wherein the additional switch is for connecting the memory management unit to the additional translation lookaside buffer when the process identifier does not match any of the plurality of process identifiers stored in the plurality of switches.

8. The device of claim 1 , wherein each of the plurality of translation lookaside buffers comprises a static random access memory for storing a plurality of entries mapping virtual memory addresses of a process of the plurality of processes to physical memory addresses of a memory device, wherein for each of the plurality of translation lookaside buffers, the process is associated with the process identifier of the plurality of process identifiers that is stored in the switch associated with the translation lookaside buffer.

9. The device of claim 1 , wherein the ranking comprises: tracking the memory utilization of the plurality of processes; ranking the memory utilization of the plurality of processes; and writing a subset of process identifiers of the plurality of process identifiers to a subset of registers of the plurality of switches when the ranking of the memory utilization of a corresponding subset of processes of the plurality of processes is greater than a threshold.

10. The device of claim 9 , wherein the memory management unit is further for: searching the translation lookaside buffer associated with one of the plurality of switches for an entry that matches a virtual memory address associated with a first process; detecting a translation lookaside buffer miss for the virtual memory address; performing a page walk in a page table stored in a memory device to find the entry that matches the virtual memory address associated with the first process; writing the entry that matches the virtual memory address associated with the first process to the translation lookaside buffer that is associated with the one of the plurality of switches when the entry that matches the virtual memory address associated with the first process is found during the page walk; and re-searching the translation lookaside buffer that is associated with the one of the plurality of switches for the entry that matches the virtual memory address associated with the first process.

11. A memory management unit comprising: hardware logic; and a non-transitory computer-readable medium storing instructions which, when executed by the hardware logic, cause the hardware logic to perform operations, the operations comprising: ranking a plurality of processes based on a memory utilization, wherein the ranking is used to assign one or more of a plurality of translation lookaside buffers to one or more of the plurality of processes; receiving a virtual memory address and a process identifier from a processor of a central processing unit; forwarding the process identifier to a plurality of switches, wherein each of the plurality of switches comprises a register for storing a different process identifier of a plurality of process identifiers, wherein each of the plurality of switches is associated with a different translation lookaside buffer of the plurality of translation lookaside buffers assigned to the processor, wherein each of the plurality of translation lookaside buffers is to be assigned to a different process of the plurality of processes of the processor, wherein each of the plurality of switches is for connecting the memory management unit to a translation lookaside buffer of the plurality of translation lookaside buffers that is associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch; accessing one of the plurality of translation lookaside buffers when the memory management unit is connected to the one of the plurality of translation lookaside buffers by one of the plurality of switches; and searching for an entry that maps the virtual memory address to a physical memory address in the one of the plurality of translation lookaside buffers.

12. The memory management unit of claim 11 , wherein the operations further comprise: retrieving the physical memory address, when the entry that maps the virtual memory address to a physical memory address is found; and accessing the physical memory address in a memory device.

13. The memory management unit of claim 11 , wherein the operations further comprise: retrieving the physical memory address, when the entry that maps the virtual memory address to the physical memory address is found; and searching a memory cache for an entry associated with the physical memory address.

14. The memory management unit of claim 11 , wherein the operations further comprise: accessing a level 2 translation lookaside buffer to find the entry that maps the virtual memory address to the physical memory address, when the entry that maps the virtual memory address to the physical memory address is not found in the one of the plurality of translation lookaside buffers.

15. The memory management unit of claim 11 , wherein the operations further comprise: performing a page walk in a page table stored in a memory device to find the entry that maps the virtual memory address to the physical memory address, when the entry that maps the virtual memory address to the physical memory address is not found in the one of the plurality of translation lookaside buffers.

16. The memory management unit of claim 11 , wherein an open collector line is coupled to the plurality of switches, wherein the open collector line controls an additional switch for connecting the memory management unit to an additional translation lookaside buffer when the process identifier does not match any of the plurality of process identifiers stored in the plurality of switches, wherein the operations further comprise: accessing the additional translation lookaside buffer when the memory management unit is connected to the additional translation lookaside buffer via the additional switch; and searching for the entry that maps the virtual memory address to the physical memory address in the additional translation lookaside buffer.

17. The memory management unit of claim 16 , wherein the additional translation lookaside buffer is for storing entries mapping virtual memory addresses to physical memory addresses for processes of the processor that are not assigned to one of the plurality of translation lookaside buffers and for which corresponding process identifiers are not stored in one of the plurality of switches.

18. The memory management unit of claim 11 , wherein the ranking comprises: tracking the memory utilization of the plurality of processes; ranking the memory utilization of the plurality of processes; and writing a subset of process identifiers of the plurality of process identifiers to a subset of registers of the plurality of switches when the ranking of the memory utilization of a corresponding subset of processes of the plurality of processes is greater than a threshold.

19. The memory management unit of claim 18 , wherein the operations further comprise: searching a translation lookaside buffer associated with one of the plurality of switches for an entry that matches a virtual memory address associated with a first process; detecting a translation lookaside buffer miss for the virtual memory address; performing a page walk in a page table stored in a memory device to find the entry that matches the virtual memory address associated with the first process; writing the entry that matches the virtual memory address associated with the first process to the translation lookaside buffer that is associated with the one of the plurality of switches when the entry that matches the virtual memory address associated with the first process is found during the page walk; and re-searching the translation lookaside buffer associated with the one of the plurality of switches for the entry that matches the virtual memory address associated with the first process.

20. A method comprising: ranking, by a memory management unit, a plurality of processes based on a memory utilization, wherein the ranking is used to assign one or more of a plurality of translation lookaside buffers to one or more of the plurality of processes; receiving, by the memory management unit, a virtual memory address and a process identifier from a processor; forwarding, by the memory management unit, the process identifier to a plurality of switches, wherein each of the plurality of switches comprises a register for storing a different process identifier of a plurality of process identifiers, wherein each of the plurality of switches is associated with a different translation lookaside buffer of a plurality of translation lookaside buffers assigned to the processor, wherein each of the plurality of translation lookaside buffers is to be assigned to a different process of a plurality of processes of the processor, wherein each of the plurality of switches is for connecting the memory management unit to a translation lookaside buffer of the plurality of translation lookaside buffers that is associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch; accessing, by the memory management unit, one of the plurality of translation lookaside buffers when the memory management unit is connected to the one of the plurality of translation lookaside buffers by one of the plurality of switches; and searching, by the memory management unit, for an entry that maps the virtual memory address to a physical memory address in the one of the plurality of translation lookaside buffers.