Timebase Synchronization

1. An apparatus comprising: a first timebase register; a first control circuit coupled to the first timebase register, wherein the first control circuit is configured to: increment a first timebase value in the first timebase register responsive to a first clock; saturate the first timebase value at a first value responsive to the first timebase value reaching the first value prior to a synchronization event; and load the first value into the first timebase register responsive to the synchronization event and to the first timebase value not reaching the first value prior to the synchronization event; a second timebase register; and a second control circuit coupled to the first control circuit and the second timebase register, wherein the second control circuit is configured to: generate the first value; generate the synchronization event responsive to a second clock and transmit an indication of the synchronization event to the first control circuit; increment a second timebase value in the second timebase register responsive to the first clock; saturate the second timebase value at the first value responsive to the second timebase value reaching the first value prior to the synchronization event; and load the first value into the second timebase register responsive to the synchronization event and to the second timebase value not reaching the first value prior to the synchronization event.

2. The apparatus as recited in claim 1 further comprising: a third timebase register; a third control circuit coupled to the third timebase register and the second control circuit, wherein the third control circuit is configured to: increment a third timebase value in the third timebase register responsive to a third clock; saturate the third timebase value at the first value responsive to the third timebase value reaching the first value prior to the synchronization event; and load the first value into the second timebase register responsive to the synchronization event and to the third timebase value not reaching the first value prior to the synchronization event; and the second control circuit is configured to transmit the indication of the synchronization event to the third control circuit.

3. The apparatus as recited in claim 2 wherein the first clock and the third clock have a same frequency, and wherein the second clock has a second frequency that is less than the same frequency.

4. The apparatus as recited in claim 1 wherein the first clock has a first frequency, and wherein the second clock has a second frequency that is less than the first frequency, and wherein a difference between the first values in consecutive synchronization events is dependent on a ratio of the first frequency to the second frequency.

5. The apparatus as recited in claim 4 wherein the synchronization event is a first edge of the second clock.

6. The apparatus as recited in claim 5 wherein the second control circuit is configured to transmit the first value to the first control circuit responsive to a second edge of the second clock, wherein the second edge is an opposite edge from the first edge, and wherein the first control circuit is configured to update the first timebase value without attempting to saturate at the first value during a time elapsing between an occurrence of the first edge and receipt of the first value.

7. The apparatus as recited in claim 6 wherein the first edge is a rising edge and the second edge is a falling edge.

8. The apparatus as recited in claim 1 wherein the first clock is generated by a first clock source and the second clock is generated by a second clock source, wherein the first clock source is subject to a first variation during use and the second clock source is subject to a second variation during use, wherein a first range of the first variation is greater than a second range of the second variation.

9. A method comprising: generating a first value by a second timebase circuit; generating a synchronization event by the second timebase circuit responsive to a first edge of a second clock; initiating a transmission from the second timebase circuit to a first timebase circuit of the first value responsive to a second edge of the second clock that is opposite the first edge; controlling the transmission at a rate of a first clock; incrementing a first timebase value in a first timebase register in the first timebase circuit responsive to the first clock; saturating the first timebase value at the first value responsive to the first timebase value reaching the first value prior to the synchronization event; loading the first value into the first timebase register responsive to the synchronization event and to the first timebase value not reaching the first value prior to the synchronization event.

10. The method as recited in claim 9 further comprising: incrementing a second timebase value in a second timebase register responsive to a third clock; saturating the second timebase value at the first value responsive to the second timebase value reaching the first value prior to the synchronization event; and loading the first value into the second timebase register responsive to the synchronization event and to the second timebase value not reaching the first value prior to the synchronization event.

11. The method as recited in claim 10 wherein the first clock and the third clock have a same frequency, and wherein the second clock has a second frequency that is less than the same frequency.

12. The method as recited in claim 9 wherein the first clock has a first frequency, and wherein the second clock has a second frequency that is less than the first frequency, and wherein a difference between the first values in consecutive synchronization events is dependent on a ratio of the first frequency to the second frequency.

13. The method as recited in claim 12 wherein controlling the transmission comprises transmitting the first value in portions, each portion of the first value transmitted at a different edge of the first clock.

14. The method as recited in claim 12 wherein controlling the transmission comprises serially transmitting the first value responsive to edges of the first clock.

15. The method as recited in claim 12 wherein the first edge is a rising edge and the second edge is a falling edge.

16. The method as recited in claim 9 further comprising: generating the first clock by a first clock source; and generating the second clock by a second clock source, wherein the first clock source is subject to a first variation and the second clock source is subject to a second variation, wherein a first range of the first variation is greater than a second range of the second variation.

17. An integrated circuit comprising: a plurality of components; a plurality of local timebase circuits, wherein a given component of the plurality of components is configured to measure time from one of the plurality of local timebase circuits, wherein each local timebase circuit of the plurality of local timebase circuits is configured to update a local timebase responsive to a first clock operating at a first clock frequency; and a global timebase circuit configured to synchronize the local timebases in the plurality of local time base circuits responsive to a second clock operating at a second clock frequency, wherein: the global timebase circuit is configured to transmit a next timebase value that will be a correct timebase at an end of a clock period of the second clock; the plurality of local timebase circuits ensure that the local timebase does not exceed the next timebase value during the clock period and that the local timebase equals the next timebase value at the end of the clock period; and the global timebase circuit includes a global timebase updated according to the first clock, wherein the global timebase circuit ensures that the global timebase does not exceed the next timebase value during the clock period and that the global timebase equals next timebase value at the end of the clock period.

18. The integrated circuit as recited in claim 17 further comprising a clock generation circuit configured to generate the first clock, and wherein the second clock is received from an input to the integrated circuit.

19. The integrated circuit as recited in claim 17 wherein the first clock has a first clock frequency and the second clock has a second clock frequency that is less than the first clock frequency, and wherein the ratio of the second clock frequency to the first clock frequency indicates a difference in consecutive next timebase values.

20. The integrated circuit as recited in claim 17 wherein the first clock is subject to a first variation during use and the second clock is subject to a second variation during use, and wherein a first range of the first variation is greater than a second range of the second variation.