Reducing Verification Checks When Programming a Memory Device

1. An apparatus, comprising: a memory controller with circuitry configured to: initiate a program verify sequence to verify data written to a non-volatile memory (NVM), said program verify sequence having one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified; detect an approximate percentage of memory cells for each program verify level in which data is successfully written; determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold; and skip the verification checks in the subsequent program pulse to reduce programming time during data write to the NVM; and one or more of: the NVM, the NVM being communicatively coupled to the memory controller; a processor communicatively coupled to the memory controller; a network interface communicatively coupled to a processor; a display communicatively coupled to a processor; or a battery coupled to a processor.

2. The apparatus of claim 1 , wherein the memory controller is configured to skip the verification checks in the subsequent program pulse to reduce programming time during data write to the NVM.

3. The apparatus of claim 1 , wherein the verification checks to be skipped in the subsequent program pulse for one or more program verify levels include at least one of: a count fail byte (CFBYTE) check, a distribution program check (DPC) or a DPC elaboration.

4. The apparatus of claim 1 , wherein the one or more program verify levels in the program verify sequence are associated with a selected word line in the NVM.

5. The apparatus of claim 1 , wherein the memory controller comprises logic further configured to detect the approximate percentage of memory cells for each program verify level in which data is successfully written during a warm up sequence of the program verify sequence.

6. The apparatus of claim 1 , wherein the memory controller comprises logic further configured to: identify a voltage drop (Va-Vb) across a resistance (rpwr) in a NVM storage device, wherein the voltage drop (Va-Vb) is represented by a current limit (Ilimit) multiplied by a number of memory cells in a defined program verify level for which data is not successfully written (no_of_fails) multiplied by the resistance (rpwr); compare the voltage drop (Va-Vb) across the resistance (rpwr) to a predefined threshold; and either determine to skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is greater than the predefined threshold; or determine to not skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is less than the predefined threshold.

7. The apparatus of claim 1 , wherein the memory controller comprises logic further configured to: identify a rate of discharge of a voltage (Vreg0) through a current limited pull down path of a NVM storage device, wherein a shielded bit line architecture is utilized in the NVM storage device; and detect the approximate percentage of memory cells in a defined program verify level for which data is successfully written based on the rate of discharge of the voltage (Vreg0) and a current limit (Ilimit).

8. The apparatus of claim 1 , wherein the memory controller comprises logic further configured to: detect, in each program verify sequence, an approximate percentage of memory cells for each program verify level in which data is successfully written; and determine whether to skip one or more verification checks in a program pulse immediately following each program verify sequence based on the approximate percentage of memory cells in relation to the defined threshold.

9. The apparatus of claim 1 , wherein the program verify sequence includes a defined number of program verify levels depending on a defined number of bits per cell utilized in the NVM.

10. The apparatus of claim 1 , wherein: the program verify sequence includes three program verify levels when the NVM utilizes two-bit per cell technology; or the program verify sequence includes seven program verify levels when the NVM utilizes three-bit per cell technology.

11. The apparatus of claim 1 , further comprising the NVM, the NVM communicatively coupled to the memory controller, the NVM to include single or multi-dimensional NAND.

12. A data storage system operable to reduce programming time during data write to memory, the data storage system comprising: a memory controller comprising logic to: initiate a program pulse to write data to a non-volatile memory (NVM); initiate a program verify sequence to verify the data written to the NVM, wherein the program verify sequence includes one or more program verify levels associated with a selected word line in the NVM and that each correspond to memory cells in the NVM for which written data is being verified; detect an approximate percentage of memory cells for each program verify level in the program verify sequence for which data is successfully written; and determine to skip one or more verification checks in one or more program verify levels of a subsequent program pulse when the approximate percentage of memory cells in which data is successfully written for one or more program verify levels in the program verify sequence is less than a defined threshold, wherein skipping the one or more verification checks in the subsequent program pulse reduces programming time during data write to the NVM; and one or more of: the NVM, the NVM being communicatively coupled to the memory controller; a processor communicatively coupled to the memory controller; a network interface communicatively coupled to a processor; a display communicatively coupled to a processor; or a battery coupled to a processor.

13. The data storage system of claim 12 , wherein the one or more verification checks to be skipped in the subsequent program pulse for one or more verify levels include at least one of: a count fail byte (CFBYTE) check, a distribution program check (DPC) or a DPC elaboration.

14. The data storage system of claim 12 , wherein the memory controller comprises logic configured to detect the approximate percentage of memory cells for each program verify level in which data is successfully written during a warm up sequence of the program verify sequence.

15. The data storage system of claim 12 , wherein the memory controller comprises logic further configured to: identify a voltage drop (Va-Vb) across a resistance (rpwr) in a NVM storage device, wherein the voltage drop (Va-Vb) is represented by a current limit (Ilimit) multiplied by a number of memory cells in a defined program verify level for which data is not successfully written (no_of_fails) multiplied by the resistance (rpwr); compare the voltage drop (Va-Vb) across the resistance (rpwr) to a predefined threshold; and either determine to skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is greater than the predefined threshold; or determine to not skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is less than the predefined threshold.

16. The data storage system of claim 12 , wherein the memory controller comprises logic further configured to: identify a rate of discharge of a voltage (Vreg0) through a current limited pull down path of NVM storage device, wherein a shielded bit line architecture is utilized in the NVM storage device; and detect the approximate percentage of memory cells in a defined program verify level for which data is successfully written based on the rate of discharge of the voltage (Vreg0) and a current limit (Ilimit).

17. The data storage system of claim 12 , wherein the memory controller comprises logic further configured to: detect, in each program verify sequence, an approximate percentage of memory cells for each program verify level in which data is successfully written; and determine whether to skip one or more verification checks in a program pulse immediately following each program verify sequence based on the approximate percentage of memory cells in relation to the defined threshold.

18. The data storage system of claim 12 , wherein the NVM is communicatively coupled to the memory controller, the NVM to include single or multi-dimensional NAND.

19. A method for reducing programming time in a non-volatile memory (NVM), the method comprising: initiating, at a memory controller, a program pulse to write data to the NVM; initiating, at the memory controller, a program verify sequence to verify the data written to the NVM, wherein the program verify sequence includes one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified; detecting, at the memory controller, an approximate percentage of memory cells for each program verify level in the program verify sequence in which data is successfully written; and determining, at the memory controller, to skip one or more verification checks in one or more program verify levels of a subsequent program pulse when the approximate percentage of memory cells in which data is successfully written for one or more program verify levels in the program verify sequence is less than a defined threshold, wherein skipping the one or more verification checks in the subsequent program pulse reduces programming time during data write to the NVM, wherein the one or more verification checks to be skipped in the subsequent program pulse for one or more verify levels include at least one of: a count fail byte (CFBYTE) check, a distribution program check (DPC) or a DPC elaboration.

20. The method of claim 19 , further comprising: identifying a voltage drop (Va-Vb) across a resistance (rpwr) in a NVM storage device, wherein the voltage drop (Va-Vb) is represented by a current limit (Ilimit) multiplied by a number of memory cells in a defined program verify level for which data is not successfully written (no_of_fails) multiplied by the resistance (rpwr); comparing the voltage drop (Va-Vb) across the resistance (rpwr) to a predefined threshold; and either determining to skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is greater than the predefined threshold; or determining to not skip the one or more verification checks in the defined program verify level of the subsequent program pulse when the voltage drop (Va-Vb) across the resistance (rpwr) is less than the predefined threshold.

21. The method of claim 19 , further comprising: identifying a rate of discharge of a voltage (Vreg0) through a current limited pull down path of a NVM storage device, wherein a shielded bit line architecture is utilized in the NVM storage device; and detecting the approximate percentage of memory cells in a defined program verify level for which data is successfully written based on the rate of discharge of the voltage (Vreg0) and a current limit (Ilimit).

22. The method of claim 19 , wherein the NVM is communicatively coupled to the memory controller, the NVM to include single or multi-dimensional NAND.