Ternary Puf Unit and Circuit Realized by Cnfet

1. A Carbon Nanotube Field Effect Transistor (CNFET) based ternary Physical Unclonable Function (PUF) unit, comprising: a 1 st CNFET transistor, a 2 nd CNFET transistor, a 3 rd CNFET transistor, a 4 th CNFET transistor, a 5 th CNFET transistor, a 6 th CNFET transistor, a 7 th CNFET transistor, an 8 th CNFET transistor, a 9 th CNFET transistor and a 10 th CNFET transistor; wherein the 1 st CNFET transistor, the 3 rd CNFET transistor, the 4 th CNFET transistor, the 5 th CNFET transistor, the 7 th CNFET transistor and the 8 th CNFET transistor are N CNFET transistors; and the 2 nd CNFET transistor, the 6 th CNFET transistor, the 9 th CNFET transistor and the 10 th CNFET transistor are P CNFET transistors; wherein a gate of the 1 st CNFET transistor is connected to a gate of the 8 th CNFET transistor which forms a first connecting terminal, and the first connecting terminal is a numerical line control signal input terminal of the said ternary PUF unit; wherein a drain of the 1 st CNFET transistor, a gate of the 2 th CNFET transistor, a gate of the 3 rd CNFET transistor, a source of the 5 th CNFET transistor, a drain of the 6 th CNFET transistor and a drain of the 7 th CNFET transistor are connected to a drain of the 9 th CNFET transistor; wherein a source of the 1 st CNFET transistor is an inverted output of the said ternary PUF unit; wherein a source of the 2 nd CNFET transistor, a source of the 9 th CNFET transistor, a source of the 10 th CNFET transistor, a source of the 6 th CNFET transistor and a gate of the 4 th CNFET transistor is connected to a gate of the 5 th CNFET transistor which forms a second connecting terminal, and the second connecting terminal is connected to a 1 st power source; wherein a drain of the 2 nd CNFET transistor, a drain of the 3 rd CNFET transistor, a source of the 4 th CNFET transistor, a drain of the 10 th CNFET transistor, a gate of the 6 th CNFET transistor and a gate of the 7 th CNFET transistor is connected to a drain of the 8 th CNFET transistor; wherein a source of the 3 rd CNFET transistor and a source of the 7 th CNFET transistor are grounded; wherein a drain of the 4 th CNFET transistor is connected to a drain of the 5 th CNFET transistor which forms a third connecting terminal, and the third connecting terminal is connected to a 2 nd power source; wherein the 2 nd power source is equivalent to half of the 1 st power source; wherein a source of the 8 th CNFET transistor is an output terminal of the said ternary PUF unit; wherein a gate of the 9 th CNFET transistor is connected to a gate of the 10 th CNFET transistor which forms a fourth connecting terminal, and the fourth connecting terminal is an enabling terminal of the said ternary PUF unit.

2. A CNFET based ternary PUF circuit, comprising: a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF unit array comprises 3 n ×3 n ternary PUF units arranged in a 3 n rows×3 n columns matrix; wherein n is an integral greater or equal to one; wherein the said ternary row decoder is provided with n input terminals and 3 n output terminals; wherein the said ternary column decoder is provided with n input terminals and 3 n output terminals; wherein the said ternary output circuit is provided with 3 n ×3″ input terminals, 3 n ×3 n inverted input terminals and 2×3 n output terminals; wherein each of the said ternary PUF unit comprises a 1 st CNFET transistor, a 2 nd CNFET transistor, a 3rd CNFET transistor, a 4 th CNFET transistor, a 5 th CNFET transistor, a 6 th CNFET transistor, a 7 th CNFET transistor, an 8 th CNFET transistor, a 9 th CNFET transistor and a 10 th CNFET transistor; wherein the 1 st CNFET transistor, the 3 rd CNFET transistor, the 4 th CNFET transistor, the 5 th CNFET transistor, the 7 th CNFET transistor and the 8 th CNFET transistor are N CNFET transistors; and the 2 nd CNFET transistor, the 6 th CNFET transistor, the 9 th CNFET transistor and the 10 th CNFET transistor are P CNFET transistors; wherein a gate of the 1 st CNFET transistor is connected to a gate of the 8 th CNFET transistor which forms a fifth connecting terminal, and the fifth connecting terminal is a numerical line control signal input terminal of the said ternary PUF unit; wherein a drain of the 1 st CNFET transistor, a gate of the 2 nd CNFET transistor, a gate of the 3 th CNFET transistor, a source of the 5 th CNFET transistor, a drain of the 6 th CNFET transistor and a drain of the 7 th CNFET transistor is connected to a drain of the 9 th CNFET transistor; wherein a source of the 1 st CNFET transistor is an inverted output terminal of the said ternary PUF unit; wherein a source of the 2 nd CNFET transistor, a source of the 9 th CNFET transistor, a source of the 10 th CNFET transistor, a source of the 6 th CNFET transistor and a gate of the 4 th CNFET transistor are connected to a gate of the 5 th CNFET transistor which forms a sixth connecting terminal, and the sixth connecting terminal is connected to a 1 st power source; wherein a drain of the 2 nd CNFET transistor, a drain of the 3 rd CNFET transistor, a source of the 4 th CNFET transistor, a drain of the 10 th CNFET transistor, a gate of the 6 th CNFET transistor and a gate of the 7 th CNFET transistor are connected to a drain of the 8 th CNFET transistor; wherein a source of the 3 rd CNFET transistor and a source of the 7 th CNFET transistor are grounded; wherein a drain of the 4 th CNFET transistor is connected to a drain of the 5 th CNFET transistor which forms a seventh connecting terminal, and the seventh connecting terminal is connected to a 2 nd power source; the 2 nd power source is equivalent to half of the power source; wherein a source of the 8 th CNFET transistor is an output terminal of the said ternary PUF unit; wherein a gate of the 9 th CNFET transistor is connected to a gate of the 10 th CNFET transistor which forms an eighth connecting terminal, and the eighth connecting terminal is an enabling terminal of the said ternary PUF unit; a numerical line control signal input terminal of the said ternary PUF unit in row j is connected to an output terminal j of the said ternary row decoder; a numerical line control signal input terminal of the said ternary PUF unit in column j is connected to an output terminal j of the said ternary column decoder, wherein j=1, 2, . . . , 3 n ; wherein 3 n ×3 n output terminals of said ternary PUF unit are in corresponding connection with 3 n ×3 n input terminals of the said ternary output circuit; and 3 n ×3 n inverted output terminals of the said ternary PUF unit are in corresponding connection with 3 n ×3 n inverted input terminals of the said ternary output circuit.