Error Processing Method, Memory Storage Device and Memory Controlling Circuit Unit

1. An error processing method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the error processing method comprising: sending a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells; performing a first decoding on the bits; if the bits have at least one error, correcting the at least one error, and determining whether each of the at least one corrected error belongs to a first type error or a second type error according to the step of the correcting the at least one error, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error; if a first error in the at least one error belongs to the first type error, recording related information of the first error; and if the first error belongs to the second type error, not recording the related information of the first error.

2. The error processing method of claim 1 , wherein the step of determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to the first error in the bits; determining whether a value of the channel reliability information is greater than a reliability threshold; and if the value of the channel reliability information is not greater than the reliability threshold, determining that the first error belongs to the second type error.

3. The error processing method of claim 1 , further comprising: sending a second read command sequence, wherein the second read command sequence is configured to read a plurality of first bits included in the bits from the memory cells; correcting the bits according to the recorded related information; and performing a second decoding on the corrected bits.

4. The error processing method of claim 1 , further comprising: accumulating a total of at least one error belonging to the first type error in the bits; determining whether the total is greater than an error threshold; and if the total is greater than the error threshold, sending a write command sequence, wherein the write command sequence is configured to write the corrected bits into the memory cells.

5. The error processing method of claim 1 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

6. An error processing method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the error processing method comprising: sending a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells; performing a first decoding on the bits; if the bits have at least one error, correcting the at least one error, and determining whether each of the at least one corrected error belongs to a first type error or a second type error according to the step of the correcting the at least one error, wherein the first type error is different from the second type error, and the step of determining whether each of the at least one error belongs to the first type error or the second type error comprises: identifying a first memory cell corresponding to a first error in the memory cells; determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to the first error in the bits is not the reference bit; if the reference bit is the first value, determining that the first error belongs to the first type error; and if the reference bit is not the first value, determining that the first error belongs to the second type error; if the first error in the at least one error belongs to the first type error, recording related information of the first error; and if the first error belongs to the second type error, not recording the related information of the first error.

7. The error processing method of claim 6 , wherein the first memory cell comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.

8. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of memory cells; and a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells, the memory controlling circuit unit is further configured to perform a first decoding on the bits, if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error, if a first error in the at least one error belongs to the first type error, the memory controlling circuit unit is further configured to record related information of the first error, and if the first error belongs to the second type error, the memory controlling circuit unit does not record the related information of the first error.

9. The memory storage device of claim 8 , wherein the operation of the memory controlling circuit unit determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to the first error in the bits; determining whether a value of the channel reliability information is greater than a reliability threshold; and if the value of the channel reliability information is not greater than the reliability threshold, determining that the first error belongs to the second type error.

10. The memory storage device of claim 8 , wherein the memory controlling circuit unit is further configured to send a second read command sequence, wherein the second read command sequence is configured to read a plurality of first bits included in the bits from the memory cells, the memory controlling circuit unit is further configured to correct the bits according to the recorded related information and perform a second decoding on the corrected bits.

11. The memory storage device of claim 8 , wherein the memory controlling circuit unit is further configured to accumulate a total of at least one error belonging to the first type error in the bits and determine whether the total is greater than an error threshold, if the total is greater than the error threshold, the memory controlling circuit unit sends a write command sequence, wherein the write command sequence is configured to write the corrected bits into the memory cells.

12. The memory storage device of claim 8 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

13. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of memory cells; and a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells, the memory controlling circuit unit is further configured to perform a first decoding on the bits, if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error, wherein the first type error is different from the second type error, and the operation of the memory controlling circuit unit determining whether each of the at least one error belongs to the first type error or the second type error comprises: identifying a first memory cell corresponding to a first error in the memory cells; determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to the first error in the bits is not the reference bit; if the reference bit is the first value, determining that the first error belongs to the first type error; and if the reference bit is not the first value, determining that the first error belongs to the second type error, wherein if the first error in the at least one error belongs to the first type error, the memory controlling circuit unit is further configured to record related information of the first error, and if the first error belongs to the second type error, the memory controlling circuit unit does not record the related information of the first error.

14. The memory storage device of claim 13 , wherein the first memory cell comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.

15. A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; an error checking and correcting circuit; and a memory management circuit coupled to the host interface, the memory interface and the error checking and correcting circuit, wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells, the error checking and correcting circuit is configured to perform a first decoding on the bits, if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error by the error checking and correcting circuit, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error, if a first error in the at least one error belongs to the first type error, the memory management circuit is further configured to record related information of the first error, and if the first error belongs to the second type error, the memory management circuit does not record the related information of the first error.

16. The memory controlling circuit unit of claim 15 , wherein the operation of the memory management circuit determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to the first error in the bits; determining whether a value of the channel reliability information is greater than a reliability threshold; and if the value of the channel reliability information is not greater than the reliability threshold, determining that the first error belongs to the second type error.

17. The memory controlling circuit unit of claim 15 , wherein the memory management circuit is further configured to send a second read command sequence, wherein the second read command sequence is configured to read a plurality of first bits included in the bits from the memory cells, the memory management circuit is further configured to correct the bits according to the recorded related information, and the error checking and correcting circuit is further configured to perform a second decoding on the corrected bits.

18. The memory controlling circuit unit of claim 15 , wherein the memory management circuit is further configured to accumulate a total of at least one error belonging to the first type error in the bits and determine whether the total is greater than an error threshold, and if the total is greater than the error threshold, the memory management circuit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into the memory cells.

19. The memory controlling circuit unit of claim 15 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

20. A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; an error checking and correcting circuit; and a memory management circuit coupled to the host interface, the memory interface and the error checking and correcting circuit, wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells, the error checking and correcting circuit is configured to perform a first decoding on the bits, if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error by the error checking and correcting circuit, wherein the first type error is different from the second type error, wherein the operation of the memory management circuit determining whether each of the at least one error belongs to the first type error or the second type error comprises: identifying a first memory cell corresponding to a first error in the memory cells; determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to the first error in the bits is not the reference bit; if the reference bit is the first value, determining that the first error belongs to the first type error; and if the reference bit is not the first value, determining that the first error belongs to the second type error, wherein if the first error in the at least one error belongs to the first type error, the memory management circuit is further configured to record related information of the first error, and if the first error belongs to the second type error, the memory management circuit does not record the related information of the first error.

21. The memory controlling circuit unit of claim 20 , wherein the first memory cell comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.

22. An error processing method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the error processing method comprising: sending a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells; performing a first decoding on the bits; if the bits have at least one error, correcting the at least one error, and determining whether each of the at least one corrected error belongs to a first type error or a second type error according to the step of correcting the at least one error, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error; if the at least one error includes the first type error, sending a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells; and if each of the at least one error belongs to the second type error, outputting the corrected bits, wherein the first memory cell is different from the second memory cell.

23. The error processing method of claim 22 , wherein the step of determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to a first error of the at least one error in the bits; and determining whether a value of the channel reliability information is greater than a reliability threshold.

24. The error processing method of claim 22 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

25. An error processing method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the error processing method comprising: sending a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells; performing a first decoding on the bits; if the bits have at least one error, correcting the at least one error, and determining whether each of the at least one corrected error belongs to a first type error or a second type error according to the step of correcting the at least one error, wherein the first type error is different from the second type error, wherein the step of determining whether each of the at least one error belongs to the first type error or the second type error comprises: determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to a first error of the at least one error in the bits is not the reference bit; and if the reference bit is the first value, determining that the first error belongs to the first type error, wherein if the at least one error includes the first type error, sending a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells; and if each of the at least one error belongs to the second type error, outputting the corrected bits, wherein the first memory cell is different from the second memory cell.

26. The error processing method of claim 25 , wherein the first memory cell comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.

27. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of memory cells; and a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells, the memory controlling circuit unit is further configured to perform a first decoding on the bits, if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error, if the at least one error includes the first type error, the memory controlling circuit unit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and if each of the at least one error belongs to the second type error, the memory controlling circuit unit is further configured to output the corrected bits, wherein the first memory cell is different from the second memory cell.

28. The memory storage device of claim 27 , wherein the operation of the memory controlling circuit unit determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to a first error of the at least one error in the bits; and determining whether a value of the channel reliability information is greater than a reliability threshold.

29. The memory storage device of claim 27 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

30. A memory storage device, comprising: a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module comprising a plurality of memory cells; and a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells, the memory controlling circuit unit is further configured to perform a first decoding on the bits, if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error, wherein the first type error is different from the second type error, wherein the operation of the memory controlling circuit unit determining whether each of the at least one error belongs to the first type error or the second type error comprises: determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to a first error of the at least one error in the bits is not the reference bit; and if the reference bit is the first value, determining that the first error belongs to the first type error, wherein if the at least one error includes the first type error, the memory controlling circuit unit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and if each of the at least one error belongs to the second type error, the memory controlling circuit unit is further configured to output the corrected bits, wherein the first memory cell is different from the second memory cell.

31. The memory storage device of claim 12 , wherein the first memory cell comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.

32. A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; an error checking and correcting circuit; and a memory management circuit, coupled to the host interface, the memory interface and the error checking and correcting circuit, wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells, the error checking and correcting circuit is configured to perform a first decoding on the bits, if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error by the error checking and correcting circuit, wherein the first type error is different from the second type error, and if a value of channel reliability information is greater than a reliability threshold, the at least one corrected error is determined belonging to the first type error, if the at least one error includes the first type error, the memory management circuit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and if each of the at least one error belongs to the second type error, the memory management circuit is further configured to output the corrected bits, wherein the first memory cell is different from the second memory cell.

33. The memory controlling circuit unit of claim 32 , wherein the operation of the memory management circuit determining whether each of the at least one error belongs to the first type error or the second type error comprises: obtaining the channel reliability information of an error bit, wherein the error bit corresponds to a first error of the at least one error in the bits; and determining whether a value of the channel reliability information is greater than a reliability threshold.

34. The memory controlling circuit unit of claim 32 , wherein the second type error is regarded as usage time of the memory cell being larger than a first threshold, or a reading count, a writing count or an erasing count of the memory cell being larger than a second threshold.

35. A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises: a host interface, configured to couple to a host system; a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells; an error checking and correcting circuit; and a memory management circuit, coupled to the host interface, the memory interface and the error checking and correcting circuit, wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells, the error checking and correcting circuit is configured to perform a first decoding on the bits, if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one corrected error belongs to a first type error or a second type error according to the operation of correcting the at least one error by the error checking and correcting circuit, wherein the first type error is different from the second type error, wherein the operation of the memory management circuit determining whether each of the at least one error belongs to the first type error or the second type error comprises: determining whether a reference bit read from the first memory cell is a first value, wherein an error bit corresponding to a first error of the at least one error in the bits is not the reference bit; and if the reference bit is the first value, determining that the first error belongs to the first type error, wherein if the at least one error includes the first type error, the memory management circuit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and if each of the at least one error belongs to the second type error, the memory management circuit is further configured to output the corrected bits, wherein the first memory cell is different from the second memory cell.

36. The memory controlling circuit unit of claim 35 , wherein the first memory comprises the error bit and the reference bit, the error bit is stored in a lower physical programming unit and the reference bit is stored in an upper physical programming unit.