Shift Register Unit, Driving Method, Gate Driving Circuit and Display Device

1. A shift register unit driving method for driving a shift register unit, the shift register unit comprising a control circuit, a first output circuit and a second output circuit, wherein the first output circuit is connected with a first signal terminal, a first node and an output terminal, respectively, and configured to output a first control signal from the first signal terminal to the output terminal under the control of the first node; the second output circuit is connected with the output terminal, a second node, a first clock signal terminal and a second signal terminal, respectively, and configured to output a second control signal from the second signal terminal to the output terminal under the control of the second node and a first clock signal from the first clock signal terminal; and the control circuit is connected with the first node, the second node, the first signal terminal, the second signal terminal, the first clock signal terminal, a second clock signal terminal and an input terminal, respectively, and configured to control the potentials of the first node and the second node under the control of the first control signal from the first signal terminal, the second control signal from the second signal terminal, the first clock signal from the first clock signal terminal, a second clock signal from the second clock signal terminal and an input signal from the input terminal, wherein the method comprises: in a first stage, the input signal inputted to the input terminal being of a second potential, the first clock signal inputted to the first clock signal terminal being of the second potential, the second clock signal inputted to the second clock signal terminal being of a first potential, the second node remaining at the second potential, and the second output circuit outputting the second control signal from the second signal terminal to the output terminal under the control of the second node, the potential of the second control signal being the second potential; in a second stage, the input signal inputted to the input terminal being of the second potential, the first clock signal inputted to the first clock signal terminal being of the first potential, the second clock signal inputted to the second clock signal terminal being of the second potential, the control circuit outputting the input signal from the input terminal to the first node, and the first output circuit outputting the first control signal to the output terminal under the control of the first node, the potential of the first control signal being the first potential; in a third stage, the input signal inputted to the input terminal being of the first potential, the first clock signal inputted to the first clock signal terminal being of the second potential, the second clock signal inputted to the second clock signal terminal being of the first potential, the first node remaining at the second potential, and the first output circuit outputting the first control signal to the output terminal under the control of the first node; and in a fourth stage, the input signal inputted to the input terminal being of the first potential, the first clock signal inputted to the first clock signal terminal being of the first potential, the second clock signal inputted to the second clock signal terminal being of the second potential, controlling the control circuit to output the second control signal from the second signal terminal to the second node, and the second output circuit outputting the second control signal to the output terminal under the control of the second node.

2. The method as claimed in claim 1 , wherein the control circuit comprises a pull-down sub-circuit, a first pull-up sub-circuit, a control sub-circuit and a second pull-up sub-circuit, and wherein the method comprises: in the third stage, the first clock signal inputted to the first clock signal terminal being of the second potential, and the pull-down sub-circuit outputting the second control signal from the second signal terminal to a fourth node; in the second stage, the input signal inputted to the input terminal being of the second potential, the first clock signal inputted to the first clock signal terminal being of the first potential, and the first pull-up sub-circuit outputting the first clock signal to a third node and the fourth node, respectively; in the second stage and the fourth stage, the second clock signal inputted to the second clock signal terminal being of the second potential, and the control sub-circuit outputting the input signal from the input terminal to the first node and outputting the potential of the fourth node to the second node; in the second stage and the third stage, the first node being of the second potential, and the second pull-up sub-circuit outputting the first control signal from the first signal terminal to the second node.

3. The method as claimed in claim 2 , wherein the pull-down sub-circuit comprises a first transistor, a second transistor and a first capacitor, and wherein the method comprises: in the first stage and the third stage, the first clock signal inputted to the first clock signal terminal being of the second potential, the second control signal inputted to the second signal terminal being of the second potential, the first transistor and the second transistor being turned on, the first capacitor storing the second potential, and the second transistor outputting the second control signal from the second signal terminal to the fourth node; and in the fourth stage, a second terminal of the second transistor remaining at the second potential, the second transistor being turned on, and the second transistor outputting the second control signal from the second signal terminal to the fourth node.

4. The method as claimed in claim 3 , wherein the transistors are all P-type transistors.

5. The method as claimed in claim 2 , wherein the first pull-up sub-circuit comprises a third transistor, a fourth transistor, a second capacitor and a fifth transistor, and wherein the method comprises: in the first stage, the input signal inputted to the input terminal being of the second potential, the first clock signal inputted to the first clock signal terminal being of the second potential, the third transistor, the fourth transistor and the fifth transistor being turned on, the second capacitor storing the second potential, the fourth transistor outputting the first clock signal from the first clock signal terminal to the third node, and the fifth transistor outputting the first clock signal to the fourth node; and in the second stage, the input signal inputted to the input terminal being of the second potential, the first clock signal inputted to the first clock signal terminal being of the first potential, the third transistor being turned off, a fifth node remaining at the second potential, the fourth transistor and the fifth transistor being turned on, the fourth transistor outputting the first clock signal from the first clock signal terminal to the third node, and the fifth transistor outputting the first clock signal to the fourth node.

6. The method as claimed in claim 2 , wherein the control sub-circuit comprises a sixth transistor and a seventh transistor, and wherein the method comprises: in the second stage and the fourth stage, the second clock signal inputted to the second clock signal terminal being of the second potential, the sixth transistor and the seventh transistor being turned on, the sixth transistor outputting the input signal from the input terminal to the first node, and the seventh transistor outputting the potential of the fourth node to the second node.

7. The method as claimed in claim 2 , wherein the second pull-up sub-circuit comprises an eighth transistor, and wherein the method comprises: in the second stage and the third stage, the first node being of the second potential, the eighth transistor being turned on, and the eighth transistor outputting the first control signal from the first signal terminal to the second node.

8. The method as claimed in claim 1 , wherein the first output circuit comprises a ninth transistor and a third capacitor, and wherein the method comprises: in the second stage, the control circuit outputting the input signal from the input terminal to the first node, the input signal being at the second potential, the ninth transistor being turned on, the third capacitor storing the second potential, and the ninth transistor outputting the first control signal from the first signal terminal to the output terminal; and in the third stage, the first node remaining at the second potential, the ninth transistor being turned on, and the ninth transistor outputting the first control signal from the first signal terminal to the output terminal.

9. The method as claimed in claim 1 , wherein the second output circuit comprises a tenth transistor and a fourth capacitor, and wherein the method comprises: in the fourth stage, the control circuit outputting the second control signal from the second signal terminal to the second node, the second control signal being of the second potential, the tenth transistor being turned on, the fourth capacitor storing the second potential, and the tenth transistor outputting the second control signal from the second signal terminal to the output terminal; and in the first stage, the second node remaining at the second potential, the tenth transistor being turned on, and the tenth transistor outputting the second control signal from the second signal terminal to the output terminal.

10. The method as claimed in claim 1 , wherein the control circuit comprises a pull-down sub-circuit, a first pull-up sub-circuit, a control sub-circuit and a second pull-up sub-circuit; and the pull-down sub-circuit is connected with the second signal terminal, the first clock signal terminal, a third node and a fourth node, respectively, and configured to output the second control signal of the second signal terminal to the fourth node under the control of the third node and the first clock signal from the first clock signal terminal; the first pull-up sub-circuit is connected with the input terminal, the first clock signal terminal, the third node and the fourth node, respectively, and configured to output the first clock signal to the third node and the fourth node, respectively, under the control of the input signal from the input terminal and the first clock signal from the first clock signal terminal; the control sub-circuit is connected with the second clock signal terminal, the input terminal, the fourth node, the first node and the second node, respectively, and configured to output the input signal from the input terminal to the first node and outputting the potential of the fourth node to the second node under the control of the second clock signal from the second clock signal terminal; and the second pull-up sub-circuit is connected with the first signal terminal, the first node and the second node, respectively, and configured to output the first control signal from the first signal terminal to the second node under the control of the first node.

11. The method as claimed in claim 10 , wherein the pull-down sub-circuit comprises a first transistor, a second transistor and a first capacitor; and a first terminal of the first transistor is connected with the second signal terminal, a second terminal of the first transistor is connected with the third node, and a third terminal of the first transistor is connected with the first clock signal terminal; a first terminal of the second transistor is connected with the second signal terminal, a second terminal of the second transistor is connected with the fourth node, and a third terminal of the second transistor is connected with the third node; and a first terminal of the first capacitor is connected with the third node, and a second terminal of the first capacitor is connected with the second signal terminal.

12. The method as claimed in claim 10 , wherein the first pull-up sub-circuit comprises a third transistor, a fourth transistor, a second capacitor and a fifth transistor; and a first terminal of the third transistor is connected with the input terminal, a second terminal of the third transistor is connected with a fifth node, and a third terminal of the third transistor is connected with the first clock signal terminal; a first terminal of the fourth transistor is connected with the first clock signal terminal, a second terminal of the fourth transistor is connected with the third node, and a third terminal of the fourth transistor is connected with the fifth node; a first terminal of the second capacitor is connected with the fifth node, and a second terminal of the second capacitor is connected with the fourth node; and a first terminal of the fifth transistor is connected with the first clock signal terminal, a second terminal of the fifth transistor is connected with the fourth node, and a third terminal of the fifth transistor is connected with the fifth node.

13. The method as claimed in claim 10 , wherein the control sub-circuit comprises a sixth transistor and a seventh transistor; and a first terminal of the sixth transistor is connected with the input terminal, a second terminal of the sixth transistor is connected with the first node, and a third terminal of the sixth transistor is connected with the second clock signal terminal; and a first terminal of the seventh transistor is connected with the fourth node, a second terminal of the seventh transistor is connected with the second node, and a third terminal of the seventh transistor is connected with the second clock signal terminal.

14. The method as claimed in claim 10 , wherein the second pull-up sub-circuit comprises an eighth transistor; and a first terminal of the eighth transistor is connected with the first signal terminal, a second terminal of the eighth transistor is connected with the second node, and a third terminal of the eighth transistor is connected with the first node.

15. The method as claimed in claim 1 , wherein the first output circuit comprises a ninth transistor and a third capacitor; and a first terminal of the ninth transistor is connected with the first signal terminal, a second terminal of the ninth transistor is connected with the output terminal, and a third terminal of the ninth transistor is connected with the first node; and a first terminal of the third capacitor is connected with the first terminal of the ninth transistor, and a second terminal of the third capacitor is connected with the third terminal of the ninth transistor.

16. The method as claimed in claim 1 , wherein the second output circuit comprises a tenth transistor and a fourth capacitor; a first terminal of the tenth transistor is connected with the second signal terminal, a second terminal of the tenth transistor is connected with the output terminal, and a third terminal of the tenth transistor is connected with the second node; and a first terminal of the fourth capacitor is connected with the third terminal of the tenth transistor, and a second terminal of the fourth capacitor is connected with the first clock signal terminal.