Computer System Including Synchronous Input/Output and Hardware Assisted Purge of Address Translation Cache Entries of Synchronous Input/Output Transactions

1. A method of purging one or more address translation cache entries included in a synchronous input/output (I/O) computing system, the method comprising: issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction; selecting a device table entry from a device table, loading the entry into a device table cache (DTC), requesting required address translation entries, installing the required address translation entries in the address translation cache and transferring data packets corresponding to the transaction using the selected device table entry and the required address translation entries; and automatically purging the address translation cache entries associated with the transaction in response to detecting that the transaction is completed, further comprising identifying at least one stale address translation cache entry in response to detecting that the transaction is completed, and automatically purging, via a host bridge, the at least one stale address translation cache entry from an address translation cache without receiving a purge command from firmware.

2. The method of claim 1 , wherein determining the at least one stale address translation cache entry includes delivering a bus number and function number corresponding to a purged device table entry to the host bridge, wherein the host bridge identifies the at least one stale address translation cache entry in the address translation cache that matches the bus number and the function number.

3. The method of claim 1 , further comprising automatically detecting an end of the transaction to identify a required address translation to purge, wherein detecting the end of the transaction comprises: monitoring, via a host bridge, the data packets transferred using the selected device table entry; and automatically purging the selected device table entry from the DTC, via the host bridge, in response to determining the transferred data packets match a total data length of a data table entry transaction.

4. The method of claim 3 , wherein the monitoring includes operating a data counter to count the data packets transferred using the selected device table entry.

5. The method of claim 4 , wherein the host bridge performs the operations of: setting the data counter to an initial value prior to transferring the data packets; decrementing the data counter each time a data packet is transferred using the device table entry; and automatically purging the selected device table entry without receiving a purge command from firmware when the data counter reaches a final value indicating the transaction is complete.

6. The method of claim 5 , wherein the initial value equals the total data length and the final value equals zero.

7. A synchronous input/output (I/O) computing system comprising a processor and a memory unit that stores program instructions, the system configured to purge one or more address translation entries in response to the processor executing the program instructions to perform: issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction; selecting a device table entry from a device table, loading the entry into a device table cache (DTC), requesting required address translation entries, installing the required address translation entries in the address translation cache and transferring data packets corresponding to the transaction using the selected device table entry and the required address translation entries; and automatically purging the address translation cache entries associated the a transaction in response to detecting that the transaction is completed, further comprising identifying at least one stale address translation cache entry in response to detecting that the transaction is completed, and automatically purging, via a host bridge, the at least one stale address translation cache entry from an address translation cache without receiving a purge command from firmware.

8. The system of claim 7 , wherein determining the at least one stale address translation cache entry includes delivering a bus number and function number corresponding to a purged device table entry to the host bridge, wherein the host bridge identifies the at least one stale address translation cache entry in the address translation cache that matches the bus number and the function number.

9. The system of claim 7 , further comprising automatically detecting an end of the transaction to identify a required address translation to purge, wherein detecting the end of the transaction comprises: monitoring, via a host bridge, the data packets transferred using the selected device table entry; and automatically purging the selected device table entry from the DTC, via the host bridge, in response to determining the transferred data packets match a total data length of a data table entry transaction.

10. The system of claim 9 , wherein the monitoring includes operating a data counter to count the data packets transferred using the selected device table entry.

11. The system of claim 10 , wherein the host bridge performs the operations of: setting the data counter to an initial value prior to transferring the data packets; decrementing the data counter each time a data packet is transferred using the device table entry; and automatically purging the selected device table entry without receiving a purge command from firmware when the data counter reaches a final value indicating the transaction is complete.

12. The system of claim 11 , wherein the initial value equals the total data length and the final value equals zero.

13. A computer program product, the computer program product comprising a non-transitory computer readable storage medium having program instructions for purging a device table cache (DTC) included in a synchronous input/output (I/O) computing system, the program instructions executable by a processor to perform: issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction; selecting a device table entry from a device table, loading the entry into the DTC, requesting required address translation entries, installing the required address translation entries in the address translation cache and transferring data packets corresponding to the transaction using the selected device table entry and the required address translation entries; and automatically purging the address translation cache entries associated with the transaction in response to detecting that the transaction is completed, further comprising identifying at least one stale address translation cache entry in response to detecting that the transaction is completed, and automatically purging, via a host bridge, the at least one stale address translation cache entry from an address translation cache without receiving a purge command from firmware.

14. The computer program product of claim 13 , wherein determining the at least one stale address translation cache entry includes delivering a bus number and function number corresponding to a purged device table entry to the host bridge, wherein the host bridge identifies the at least one stale address translation cache entry in the address translation cache that matches the bus number and the function number.

15. The computer program product of claim 13 , further comprising automatically detecting an end of the transaction to identify a required address translation to purge, wherein detecting the end of the transaction comprises: monitoring, via a host bridge, the data packets transferred using the selected device table entry; and automatically purging the selected device table entry from the DTC, via the host bridge, in response to determining the transferred data packets match a total data length of a data table entry transaction.

16. The computer program product of claim 15 , wherein the monitoring includes operating a data counter to count the data packets transferred using the selected device table entry.

17. The computer program product of claim 16 , wherein the host bridge performs the operations of: setting the data counter to an initial value prior to transferring the data packets, the initial value equaling the total data length and a final value equals zero; decrementing the data counter each time a data packet is transferred using the device table entry; and automatically purging the selected device table entry without receiving a purge command from firmware when the data counter reaches the final value indicating the transaction is complete.