Display System

1. A device for controlling a display system, the device comprising: a memory comprising a first lookup table (LUT) including a plurality of entries, where each entry includes a frame number of a corresponding one of a plurality of sequential frames, a first value, and a second value and where the first and second values are natural numbers; a controller configured to count at least one pulse of a received vertical synchronization (VSYNC) signal to obtain a frame number that corresponds to one of the plurality of sequential frames, access one of the entries of the first LUT using the obtained frame number to obtain the corresponding first and second values, and change a value of M to the obtained first value and change a value of N to the obtained second value in synchronization with a pulse of the received VSYNC signal; a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of the changed value of N to the changed value of M; and a display controller configured to adjust a frame rate of the display system according to the pixel clock signal, wherein the frame rate is a certain number of frames per second calculated by multiplying the changed value of N by the changed value of M and dividing a result of the multiplying by 60.

2. The device of claim 1 , wherein the controller receives a scenario signal relating to an operation scenario of the display system and refers to one of the first look-up table and a second other look-up table of the memory according to the scenario signal.

3. The device of claim 1 , wherein the controller changes the values of M and N within a sync period while the pulse occurs in the VSYNC signal and the fractional divider changes a frequency of the pixel clock signal in the sync period according to the changed values of M and N.

4. The device of claim 1 , wherein the controller transmits a reference request signal to the memory to access the first LUT, and wherein the reference request signal includes the obtained frame number, information about whether to increase or decrease the frequency of the pixel clock signal, and a target frequency according to the change in the frequency of the pixel clock signal.

5. The device of claim 1 , wherein the device is implemented as one of an application processor or a system-on-chip, and the display system is implemented as a television system.

6. The device of claim 1 , wherein the device is implemented as an application processor, and wherein the controller and the fractional divider are comprised in a clock management unit of the application processor.

7. The device of claim 1 , wherein the first value and the second value are different from one another and both greater than 1.

8. A display system comprising: a display device configured to display images only outside a period while a pulse occurs within a vertical synchronization (VSYNC) signal; a first controller configured to generate the VSYNC signal and output image data to the display device according to a pixel clock signal; a second controller that is configured to count at least one pulse of the VSYNC signal to obtain a frame number that corresponds to one of a plurality of sequential frames, retrieve a first value and a second value from an entry in a lookup table corresponding to the obtained frame number, and change a value of N to the retrieved first value and change a value of M to the retrieved second value, where the retrieved first and second values are natural numbers; and a fractional divider configured to divide an input clock signal by a division ratio of the changed value of N to the changed value of M only within the period to generate the pixel clock signal, wherein the first controller is configured to adjust a frame rate of the display system according to the pixel clock signal, wherein the frame rate is a certain number of frames per second calculated by multiplying the changed value of N by the changed value of M and dividing a result of the multiplying by 60.

9. The display system of claim 8 , wherein a value of a frequency of the pixel clock signal is proportional to a value of a frame rate of the display device.

10. The display system of claim 8 , wherein the second controller is configured to change the values of the N and M only within the period.

11. The device system of claim 8 , wherein the retrieved first value and the retrieved second value are different from one another and both greater than 1.