Legal claims defining the scope of protection, as filed with the USPTO.
1. A shift register, comprising: a first feedback module; a pull-down module; and a first pull-up module, wherein: the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register, and the first pull-up module has an output terminal connected to the first node and is configured to control connection of a second level signal input terminal with the first node in accordance with a first direct current signal input terminal and a second direct current signal input terminal.
2. The shift register according to claim 1 , wherein the shift register further comprises a control module, the first feedback module comprises two feedback units, which are a first feedback unit and a second feedback unit, the different control points are a second node and a third node, the control module has an output terminal connected to the second node and is configured to control a level of the second node, a control terminal of the first feedback unit is connected to the second node, a control terminal of the second feedback unit is connected to the third node, and the third node is connected to the signal output terminal.
3. The shift register according to claim 2 , wherein the first feedback unit comprises a first transistor, whose control terminal is connected to the second node, first terminal is connected to the first level input terminal, and second terminal is connected to the first node; the second feedback unit comprises a second transistor whose control terminal is connected to the third node, first terminal is connected to the first level input terminal, and second terminal is connected to the first node.
4. The shift register according to claim 2 , wherein the control module comprises a first control unit and a second control unit, the first control unit has a control terminal connected to a start signal input terminal, an input terminal connected to the first direct current signal input terminal and an output terminal connected to the second node, and the second control unit has a control terminal connected to a reset signal input terminal, an input terminal connected to the second direct current signal input terminal, and an output terminal connected to the second node.
5. The shift register according to claim 4 , wherein the first control unit comprises a third transistor, the second control unit comprises a fourth transistor, the third transistor has a control terminal connected to the start signal input terminal, a first terminal connected to the first direct current signal input terminal, and a second terminal connected to the second node, and the fourth transistor has a control terminal connected to the reset signal input terminal, a first terminal connected to the second direct current signal input terminal, and a second terminal connected to the second node.
6. The shift register according to claim 1 , wherein the pull-down module comprises a fifth transistor and a first capacitor, the fifth transistor has a control terminal connected to the first node, a first terminal connected to the first level input terminal, and a second terminal connected to the signal output terminal, and two electrode plates of the first capacitor are connected to the first node and the first level input terminal respectively.
7. The shift register according to claim 2 , wherein the shift register further comprises a second feedback module, whose control terminal is connected to the first node, input terminal is connected to the first level input terminal, and output terminal is connected to the second node.
8. The shift register according to claim 7 , wherein the second feedback module comprises a sixth transistor, whose control terminal is connected to the first node, first terminal is connected to the first level input terminal, and second terminal is connected to the second node.
9. The shift register according to claim 1 , wherein the first pull-up module comprises a seventh transistor, an eighth transistor and a ninth transistor, the seventh transistor has a control terminal connected to the first direct current signal input terminal, a first terminal connected to a second clock signal input terminal, and a second terminal connected to a control terminal of the ninth transistor; the eighth transistor has a control terminal connected to the second direct current signal input terminal, a first terminal connected to a fourth clock signal input terminal, and a second terminal connected to the control terminal of the ninth transistor; and the ninth transistor has a first terminal connected to the first node, and a second terminal connected to the second level signal input terminal.
10. The shift register according to claim 2 , wherein the shift register further comprises a second pull-up module, and the second pull-up module has an output terminal is connected to the signal output terminal and is configured to control connection of the first clock signal input terminal with the signal output terminal.
11. A gate driving circuit, comprising the shift register according to claim 1 , wherein all of shift registers are connected in cascades mutually.
12. A display apparatus, comprising the gate driving circuit according to claim 11 .
13. A driving method of a shift register used to drive the shift register according to claim 1 , comprising: controlling different feedback units comprised in the first feedback module through different control points, so as to control a potential of the first node, controlling the pull-down module through the first node, and controlling connection of the first level input terminal with the signal output terminal.
14. The driving method of the shift register according to claim 13 , wherein the shift register further comprises a control module, the first feedback module comprises two feedback units, which are a first feedback unit and a second feedback unit, and the controlling different feedback units through different control points comprises: the different control points being a second node and a third node; controlling the second node through an output terminal of the control module, and controlling the first feedback unit through the second node, so as to control connection of the first level input terminal with the signal output terminal; and controlling the third node through the signal output terminal, controlling the second feedback unit through the third node, and controlling connection of the first level input terminal with the first node, so as to control the connection of the first level input terminal with the signal output terminal.
15. The gate driving circuit according to claim 11 , further comprising a control module, wherein the first feedback module comprises two feedback units, which are a first feedback unit and a second feedback unit, the different control points are a second node and a third node, the control module has an output terminal connected to the second node, and is configured to control a level of the second node, a control terminal of the first feedback unit is connected to the second node, a control terminal of the second feedback unit is connected to the third node, and the third node is connected to the signal output terminal.
16. The gate driving circuit according to claim 15 , wherein the first feedback unit comprises a first transistor, whose control terminal is connected to the second node, first terminal is connected to the first level input terminal, and second terminal is connected to the first node; the second feedback unit comprises a second transistor, whose control terminal is connected to the third node, first terminal is connected to the first level input terminal, and second terminal is connected to the first node.
17. The gate driving circuit according to claim 15 , wherein the control module comprises a first control unit and a second control unit, the first control unit has a control terminal connected to a start signal input terminal, an input terminal connected to a first direct current signal input terminal and an output terminal connected to the second node, and the second control unit has a control terminal connected to a reset signal input terminal, an input terminal connected to a second direct current signal input terminal, and an output terminal connected to the second node.
18. The shift register according to claim 17 , wherein the first control unit comprises a third transistor, the second control unit comprises a fourth transistor, the third transistor has a control terminal connected to the start signal input terminal, a first terminal connected to the first direct current signal input terminal, and a second terminal connected to the second node, and the fourth transistor has a control terminal connected to the reset signal input terminal, a first terminal connected to the second direct current signal input terminal, and a second terminal connected to the second node.
19. The shift register according to claim 10 , wherein the second pull-up module comprises a tenth transistor, an eleventh transistor and a second capacitor, the tenth transistor has a control terminal connected to the second level input terminal, a first terminal connected to the second node, and a second terminal connected to a control terminal of the eleventh transistor, the eleventh transistor has a first terminal connected to the first clock signal input terminal, and a second terminal connected to the signal output terminal, and two electrode plates of the second capacitor are connected to the second node and the first level input terminal respectively, and a product of length and width of a channel of the eleventh transistor is at least two times of that of the tenth transistor.
20. A shift register, comprising: a first feedback module; and a pull-down module, wherein: the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register, wherein the shift register further comprises a control module, the first feedback module comprises two feedback units, which are a first feedback unit and a second feedback unit, the different control points are a second node and a third node, the control module has an output terminal connected to the second node and is configured to control a level of the second node, a control terminal of the first feedback unit is connected to the second node, a control terminal of the second feedback unit is connected to the third node, and the third node is connected to the signal output terminal, wherein the shift register further comprises a second pull-up module, and the second pull-up module has an output terminal is connected to the signal output terminal and is configured to control connection of the first clock signal input terminal with the signal output terminal, wherein the second pull-up module comprises a tenth transistor, an eleventh transistor and a second capacitor, the tenth transistor has a control terminal connected to the second level input terminal, a first terminal connected to the second node, and a second terminal connected to a control terminal of the eleventh transistor, the eleventh transistor has a first terminal connected to the first clock signal input terminal, and a second terminal connected to the signal output terminal, and two electrode plates of the second capacitor are connected to the second node and the first level input terminal respectively, and a product of length and width of a channel of the eleventh transistor is at least two times of that of the tenth transistor.
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October 23, 2018
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