10116952

Bitstream Decoding Method and Bitstream Decoding Circuit

PublishedOctober 30, 2018
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
14 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for decoding a bitstream, the bitstream comprising a plurality of frames, the method comprising: receiving the bitstream at a decoding circuit, which performs steps of: obtaining a display order of a current frame in the bitstream by parsing a header of the current frame, the current frame belonging to a group; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame, wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame comprises: determining whether the display order of the current frame is later than display orders of previous frames in the group according to the display order of the current frame, and decoding the current frame according to a determination result indicating that the display order of the current frame is later than the display orders of all the previous frames in the group thereby ensuring that at least all P-frames of the group are decoded and not dropped.

2

2. The method according to claim 1 , further comprising: obtaining one or multiple reference frames of the current frame by parsing the header of the current frame in the bitstream; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame.

3

3. The method according to claim 2 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame comprises: determining whether the current frame jointly refers to the frame having previous and adjacent display orders and the frame having a next display order in the group according to the one or multiple reference frames.

4

4. The method according to claim 3 , further comprising: dropping instead of decoding the current frame according to a determination result indicating that the current frame jointly refers to the frame having the previous and adjacent display orders and the frame having the next display order in the group.

5

5. The method according to claim 1 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame according the display order of the current frame comprises: determining whether the display order of the current frame is an integral multiple of a value according to the display order of the current frame.

6

6. The method according to claim 5 , further comprising: decoding the current frame according to a determination result indicating that the display order of the current frame is an integral multiple of the value.

7

7. The method according to claim 5 , further comprising: dropping instead of decoding the current frame according to a determination result indicating that the display order of the current frame is not an integral multiple of the value.

8

8. A bitstream decoding circuit, comprising: a decoder, accessing a bitstream comprising a plurality of frames; and a control unit, coupled to the decoder, performing steps of: obtaining a display order of a current frame in the bitstream by parsing a header of the current frame, the current frame belonging to a group; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame, wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame comprises: determining whether the display order of the current frame is later than display orders of previous frames in the group according to the display order of the current frame wherein the control unit further performs a step of: controlling the decoder to decode the current frame according to a determination result indicating that the display order of the current frame is later than the display orders of all the previous frames in the group thereby ensuring that at least all P-frames of the group are decoded and not dropped.

9

9. The bitstream decoding circuit according to claim 8 , wherein the control unit further performs a step of: obtaining one or multiple reference frames of the current frame by parsing the header of the current frame in the bitstream; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame.

10

10. The bitstream decoding circuit according to claim 9 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the one or multiple reference frames of the current frame comprises: determining whether the current frame jointly refers to the frame having previous and adjacent display orders and the frame having a next display order in the group according to the one or multiple reference frames.

11

11. The bitstream decoding circuit according to claim 10 , wherein the control unit further performs a step of: dropping instead of decoding the current frame according to a determination result indicating that the current frame jointly refers to the frame having the previous and adjacent display orders and the frame having the next display order in the group.

12

12. The bitstream decoding circuit according to claim 8 , wherein the step of determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame according the display order of the current frame comprises: determining whether the display order of the current frame is an integral multiple of a value according to the display order of the current frame.

13

13. The bitstream decoding circuit according to claim 12 , wherein the control unit further performs a step of: decoding the current frame according to a determination result indicating that the display order the current frame is an integral multiple of the value.

14

14. The bitstream decoding circuit according to claim 12 , wherein the control unit further performs a step of: dropping instead of decoding the current frame according to a determination result indicating that the display order of the current frame is not an integral multiple of the value.

Patent Metadata

Filing Date

Unknown

Publication Date

October 30, 2018

Inventors

He-Yuan LIN
Ya-Ting YANG
Yi-Shin TUNG

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Cite as: Patentable. “BITSTREAM DECODING METHOD AND BITSTREAM DECODING CIRCUIT” (10116952). https://patentable.app/patents/10116952

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