Configurable Power Management Integrated Circuit

1. A method of providing a power management system, comprising: receiving power requirements corresponding to a target device; providing implementation options to achieve the power requirements; selecting a solution from the implementation options; generating a programming file for a power management integrated circuit, the power management integrated circuit including: a plurality of cells, each cell including a pair of series-coupled switching elements, and a switch matrix and controller coupled to the plurality of cells, the switch matrix and controller configured to couple one or more of the plurality of cells together to form one or more individual power channels in response to programming signals, each power channel including at least one cell of the plurality of cells; and generating a printed circuit board design for the power management integrated circuit.

2. The method of claim 1 , wherein each power channel is coupled to components mounted on the printed circuit board in the printed circuit board design to provide a rail to a target device.

3. The method of claim 1 , wherein the power management integrated circuit further includes at least one driver coupled to each switching element in the pair of series-coupled switching elements.

4. The method of claim 3 , wherein each driver of the at least one driver includes an amplifier and a slew-rate adjust circuit.

5. The method of claim 3 , wherein an output signal from each driver of the at least one driver is switchably output to an I/O pin of the power management integrated circuit.

6. The method of claim 5 , wherein the output signal from each drive is coupled to an external switching device.

7. The method of claim 6 , wherein the cell further includes a programmable element that is configurable to couple the output signal from the driver to an I/O pin of the power management integrated circuit or to couple the output signal from the driver to the external switching device.

8. The method of claim 1 , wherein at least one of the pair of series-coupled switching devices is an FET, the source and drain of which are coupled to I/O pins.

9. The method of claim 8 , wherein the FET includes a plurality of individual FETs and the switching device can be programmed to include any of the plurality of individual FETs.

10. The method of claim 9 , wherein each cell is configurable to adjust performance of the cell.

11. The method of claim 1 , wherein each the pair of series-coupled switching elements includes a higher switching element and a lower switching element.

12. The method of claim 11 , wherein the higher switching element is a high FET and the at least one driver includes a high driver coupled to the high FET and the lower switching element is a low FET and the at least one driver includes a low driver coupled to the low FET.

13. The method of claim 12 , wherein the high FET and the low FET are coupled in series to provide an output signal between the high FET and the low FET.

14. The method of claim 13 , wherein the output signals from multiple cells are combined to complete a buck converter.

15. The method of claim 11 , wherein the lower switching element is a diode.

16. The method of claim 11 , wherein the higher switching element is a diode.

17. The method of claim 11 , wherein the switch matrix and control block includes a plurality of controllers coupled to a switch matrix.

18. The method of claim 13 , wherein the output signals from multiple cells are combined to complete a buck/boost converter.

19. The method of claim 13 , wherein multiple cells are coupled as a cascode.

20. The method of claim 17 , wherein the switch matrix is programmable to establish one or more power channels, each power channel including one or more cells, a switching matrix, and an assigned controller.

21. The method of claim 20 , wherein the higher switching element is a high FET and the lower switching element is a low FET and wherein the switch matrix for each power channel includes: a high programmable logic circuit that determines whether a gate voltage of one or more of the high FETs of cells included in the power channel is a high voltage; a low programmable logic circuit that determines whether a gate voltage of one or more of the low FETs of cells included in the power channel is a high voltage; a non-overlap circuit that receives a high logic signal from the high programmable logic circuit, a low logic signal from the low programmable logic circuit, and a pulse-wave signal from the assigned controller from the plurality of controllers and provides a high gate signal and a low gate signal; a high gate output circuit that provides a high gate signal to the high element of each cell included in the power channel; and a low gate output circuit that provides a low gate signal to the low element of each cell included in the power channel.

22. The method of claim 21 , wherein the switching matrix further includes a multiplexer that receives pulse-wave signals from more than one of the plurality of controllers, the multiplexer capable of dynamically selecting from the more than one controller to provide the pulse-wave signal to the non-overlap block.

23. The method of claim 22 , wherein the control circuit includes a processor operating a state machine.

24. The method of claim 23 , wherein the state machine includes a configuration state where programming instructions are received for each power channel.

25. The method of claim 23 , wherein the state machine includes a channel state machine for each of the power channels, the channel state machine including: an idle state where a feedback signal is zero and the circuit is not enabled; a soft-start state that is transitioned to from the idle state when the circuit becomes enabled, the soft-start state operating the circuit to raise the feedback signal to a reference value; a run state that is transitioned to from the soft-start state when the feedback signal is the reference signal, the run state operating the circuit to produce power on the power channel; and a shut-down state that is transitioned to whenever the circuit becomes not enabled or an error condition is detected.

26. The method of claim 20 , wherein the controller includes: an error amplifier that receives a feedback signal from the output signal from the power channel and provides an error signal; a ramp generator that provides a ramp voltage; a comparator that compares the ramp voltage with the error signal to form a compared signal; an oscillator that provides a pulse signal; a logic circuit that receives the pulse signal and the compare signal and provides a logic signal; and a flip-flop that receives the logic signal and provides a pulse-wave signal to the switch matrix.

27. The method of claim 26 , wherein the controller further includes a voltage reference generator that generates a reference voltage for the error amplifier.

28. The method of claim 26 , wherein the logic circuit receives an on-time pulse and an off-time pulse from the oscillator.

29. The method of claim 26 , wherein the controller further includes a thermal sensor input to the logic circuit.

30. The method of claim 26 , wherein the controller further includes an over-current protection signal input to the logic circuit.

31. The method of claim 1 , wherein the power management integrated circuit includes programmable elements that are programmed to form the at least one power channel.

32. The method of claim 31 , wherein the programmable elements include one or more of non-volatile memory, registers, and fuses.

33. The method of claim 32 , wherein the programmable elements are programmed to determine operation of each power channel in the circuit.

34. The method of claim 1 , further including programming the power management integrated circuit with the programming file.

35. The method of claim 1 , further including receiving new power requirements corresponding to a redefined target device and generating a new programming file and new printed circuit board design.

36. The method of claim 35 , wherein new power requirements result from analysis of a system based on the programming file and the printed circuit design.