Semiconductor Device

1. A semiconductor device comprising: a memory region having a plurality of memory cells; a read circuit capable of switching between a first reading method, by comparing current flowing in a memory cell to be read of the plurality of memory cells with a reference current, and a second reading method, by comparing currents flowing in first and second memory cells in which complementary data to be read is stored, of the plurality of memory cells; a register configured to set a security state; a mode controller configured to set a mode; and a control circuit configured to switch the read circuit between the first and second reading methods based on the mode set by the mode controller and the security state set by the register.

2. The semiconductor device according to claim 1 , wherein the first reading method is a reference current reading method, the second reading method is a complementary reading method.

3. The semiconductor device according to claim 1 , wherein the first and the second memory cells are complementary cells.

4. The semiconductor device according to claim 1 , wherein the control circuit switches the read circuit between the first and second reading methods based on a first signal corresponding to a boot mode from the mode controller and a second signal corresponding to a read inhibition flag from the register.

5. A semiconductor device comprising: a memory region having a plurality of complementary cells, each having first and second storing elements holding binary data according to differences in threshold voltages; and an erasure control circuit configured to initialize the complementary cells, wherein the memory region includes a normal region, and wherein, when initializing the normal region, the erasure control circuit is configured to: change threshold voltages of both the first and second storing elements of the complementary cells in the normal region to be greater than or equal to a first write level, and change the threshold voltages of both of the first and second storing elements of the complementary cells in the normal region to be less than or equal to the initialization level.

6. The semiconductor device according to claim 5 , wherein the memory region further includes a security region, and wherein, when initializing the security region, the erasure control circuit is configured to: change the threshold voltage of the second storing elements of the complementary cells in the security region to an intermediate level lower than the first write level and higher than the initialization level, change the threshold voltage of the second storing elements of the complementary cells in the security region to be greater than or equal to the first write level, change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be greater than or equal to the first write level, and change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be less than or equal to the initialization level.

7. The semiconductor device according to claim 6 , wherein the erasure control circuit is configured to carry out initialization of the normal region different from that of the security region based on respective addresses of the memory cells in the normal and security regions.

8. The semiconductor device according to claim 5 , further comprising: a register configured to receive data corresponding to a security state, wherein the data corresponding to the security state is set based on setting information stored in the security region of the memory region.

9. The semiconductor device according to claim 8 , wherein, when the data corresponding to the security state is in a first state, when initializing the security region, the erasure control circuit is configured to: change the threshold voltage of the second storing elements of the complementary cells in the security region to an intermediate level lower than the first write level and higher than the initialization level, change the threshold voltage of the second storing elements of the complementary cells in the security region to be greater than or equal to the first write level, change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be greater than or equal to the first write level, and change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be less than or equal to the initialization level.

10. The semiconductor device according to claim 9 , wherein, when the data corresponding to the security state is in a second state, when initializing the security region, the erasure control circuit is configured to: change threshold voltages of both the first and second storing elements of the complementary cells in the normal region to be greater than or equal to a first write level, and change the threshold voltages of both of the first and second storing elements of the complementary cells in the normal region to be less than or equal to the initialization level.

11. A semiconductor device comprising: a memory region having a plurality of complementary cells, each having first and second storing elements each holding binary data according to differences in threshold voltages; and an erasure control circuit configured to initialize the complementary cells, wherein the memory region includes a security region, and wherein, when initializing the security region, the erasure control circuit is configured to: change the threshold voltage of the second storing elements of the complementary cells in the security region to an intermediate level which is lower than a first write level and higher than an initialization level, change the threshold voltage of second storing element of the complementary cells in the security region to be greater than or equal to the first write level, change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be greater than or equal to the first write level, and change threshold voltages of both of the first and second storing elements of the complementary cells in the security region to be less than or equal to the initialization level.

12. The semiconductor device according to claim 11 , wherein the memory region further includes a normal region, and wherein the erasure control circuit is configured to carry out an initialization of the security region based on addresses of memory cells in the security region.